ATMEGA8L ATMEL [ATMEL Corporation], ATMEGA8L Datasheet - Page 51

• Manufacturer Part Number: ATMEGA8L
• Description: 8-bit AVR with 8K Bytes In-System Programmable Flash
• Manufacturer: ATMEL [ATMEL Corporation]

Reading the Pin Value
2486M–AVR–12/03
When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn,
PORTxn} = 0b11), an intermediate state with either pull-up enabled ({DDxn, PORTxn} =
0b01) or output low ({DDxn, PORTxn} = 0b10) must occur. Normally, the pull-up
enabled state is fully acceptable, as a high-impedant environment will not notice the dif-
ference between a strong high driver and a pull-up. If this is not the case, the PUD bit in
the SFIOR Register can be set to disable all pull-ups in all ports.
Switching between input with pull-up and output low generates the same problem. The
user must use either the tri-state ({DDxn, PORTxn} = 0b00) or the output high state
({DDxn, PORTxn} = 0b11) as an intermediate step.
Table 20 summarizes the control signals for the pin value.
Table 20. Port Pin Configurations
Independent of the setting of Data Direction bit DDxn, the port pin can be read through
the PINxn Register Bit. As shown in Figure 22, the PINxn Register bit and the preceding
latch constitute a synchronizer. This is needed to avoid metastability if the physical pin
changes value near the edge of the internal clock, but it also introduces a delay. Figure
23 shows a timing diagram of the synchronization when reading an externally applied
pin value. The maximum and minimum propagation delays are denoted t
t
Figure 23. Synchronization when Reading an Externally Applied Pin Value
INSTRUCTIONS
pd,min
DDxn
SYSTEM CLK
SYNC LATCH
0
0
0
1
1
, respectively.
PORTxn
PINxn
0
1
1
0
1
r17
(in SFIOR)
PUD
X
X
X
0
1
XXX
Output
Output
Input
Input
Input
I/O
t
Pull-up
pd, max
Yes
No
No
No
No
0x00
XXX
t
Comment
Tri-state (Hi-Z)
Pxn will source current if external
pulled low.
Tri-state (Hi-Z)
Output Low (Sink)
Output High (Source)
pd, min
in r17, PINx
ATmega8(L)
pd,max
0xFF
and
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