ATMEGA8L ATMEL [ATMEL Corporation], ATMEGA8L Datasheet - Page 122

• Manufacturer Part Number: ATMEGA8L
• Description: 8-bit AVR with 8K Bytes In-System Programmable Flash
• Manufacturer: ATMEL [ATMEL Corporation]

Serial Peripheral
Interface – SPI
122
ATmega8(L)
The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer
between the ATmega8 and peripheral devices or between several AVR devices. The
ATmega8 SPI includes the following features:
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Figure 57. SPI Block Diagram
Note:
The interconnection between Master and Slave CPUs with SPI is shown in Figure 58.
The system consists of two Shift Registers, and a Master clock generator. The SPI Mas-
ter initiates the communication cycle when pulling low the Slave Select SS pin of the
desired Slave. Master and Slave prepare the data to be sent in their respective Shift
Registers, and the Master generates the required clock pulses on the SCK line to inter-
change data. Data is always shifted from Master to Slave on the Master Out – Slave In,
MOSI, line, and from Slave to Master on the Master In – Slave Out, MISO, line. After
each data packet, the Master will synchronize the Slave by pulling high the Slave Select,
SS, line.
Full-duplex, Three-wire Synchronous Data Transfer
Master or Slave Operation
LSB First or MSB First Data Transfer
Seven Programmable Bit Rates
End of Transmission Interrupt Flag
Write Collision Flag Protection
Wake-up from Idle Mode
Double Speed (CK/2) Master SPI Mode
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DIVIDER
1. Refer to “Pin Configurations” on page 2, and Table 22 on page 56 for SPI pin
placement.
(1)
2486M–AVR–12/03