HYB18T512160AC-37 INFINEON [Infineon Technologies AG], HYB18T512160AC-37 Datasheet - Page 79

• Manufacturer Part Number: HYB18T512160AC-37
• Description: 512-Mbit Double-Data-Rate-Two SDRAM
• Manufacturer: INFINEON [Infineon Technologies AG]

6.1
For testing the
Table 38
Parameter
CAS Latency
Clock Cycle Time
Active to Read or Write delay
Active to Active / Auto-Refresh command
period
Active bank A to Active bank B command
delay
Active to Precharge Command
Precharge Command Period
Auto-Refresh to Active / Auto-Refresh
command period
1)
2)
6.2
The ODT function adds additional current consumption
to the DDR2 SDRAM when enabled by the EMRS(1).
Depending on address bits A6 & A2 in the EMRS(1) a
“week” or “strong” termination can be selected. The
.
Table 39
ODT Current
Enabled ODT current per DQ
added
ODT is HIGH; Data Bus inputs are FLOATING
Active ODT current per DQ
added
ODT is HIGH; worst case of Data Bus inputs are
STABLE or SWITCHING.
Note: For power consumption calculations the ODT duty cycle has to be taken into account
Data Sheet
4 & 8 (1 kB page size)
16 (2 kB page size)
I
I
DDQ
DDQ
current for ODT enabled;
current for ODT enabled;
I
IDD Measurement Test Condition
On Die Termination (ODT) Current
ODT current per terminated input pin:
DD
I
DD
Test Conditions
parameters, the following timing parameters are used:
Symbol
CL
t
t
t
t
t
t
t
CKmin
RCDmin
RCmin
RRDmin
RASmin
RPmin
RFCmin
min
I
I
ODTO
ODTT
79
-3.7
DDR2–533 4–4–4 DDR2–400 3–3–3
4
3.75
15
60
7.5
10
45
15
105
EMRS(1) State min.
A6 = 0, A2 = 1
A6 = 1, A2 = 0
A6 = 0, A2 = 1
A6 = 1, A2 = 0
current consumption for any terminated input pin,
depends on the input pin is in tri-state or driving “0” or
“1”, as long a ODT is enabled during a given period of
time.
512-Mbit Double-Data-Rate-Two SDRAM
HYB18T512[400/800/160]A[C/F]–[3.7/5]
5
2.5
10
5
I
-5
3
5
15
55
7.5
10
40
15
105
DD
Specifications and Conditions
typ.
6
3
12
6
09112003-SDM9-IQ3P
max.
7.5
3.75
15
7.5
Rev. 1.13, 2004-05
Units
t
ns
ns
ns
ns
ns
ns
ns
ns
CK
Unit
mA/DQ
mA/DQ
mA/DQ
mA/DQ
Notes
1)
2)