HYB18T512160AC-37 INFINEON [Infineon Technologies AG], HYB18T512160AC-37 Datasheet - Page 25

• Manufacturer Part Number: HYB18T512160AC-37
• Description: 512-Mbit Double-Data-Rate-Two SDRAM
• Manufacturer: INFINEON [Infineon Technologies AG]

2.2.3
The Extended Mode Register EMRS(1) stores the data
for enabling or disabling the DLL, output driver
strength, additive latency, OCD program, ODT, DQS
and output buffers disable, RQDS and RDQS enable.
The default value of the extended mode register
EMRS(1) is not defined, therefore the extended mode
register must be written after power-up for proper
operation. The extended mode register is written by
asserting low on CS, RAS, CAS, WE, BA1 and high on
EMR(1)
Extended Mode Register Definition
1) A13 is only available for 4 and 8 configuration.
Field
DLL
DIC
R
AL
Data Sheet
BA1
TT
0
reg. addr
BA0
1
Bits
0
1
2,6
[5:3]
DDR2 SDRAM Extended Mode Register Set (EMRS(1))
A13
0
1)
Type
w
w
w
w
OFF
A12
1)
Q
Description
DLL Enable
The DLL must be enabled for normal operation. See .
0
1
Off-chip Driver Impedance Control
0
1
Nominal Termination Resistance of ODT
Note: All other bit combinations are RESERVED.
00
10
01
Additive Latency
The additive latency must be programmed into the device to delay all read and write
commands; see
Note: All other bit combinations are RESERVED.
000 0
001 1
010 2
011 3
100 4
RDQS DQS
A11
w
Enable
Disable
Normal (Driver Size = 100%)
Weak (Driver Size = 60%)
75 Ohm
150 Ohm
(ODT disabled)
A10
w
Chapter
A9
OCD Program
(BA[1:0] = 01
A8
w
2.5.
25
BAO, while controlling the state of the address pins.
The DDR2 SDRAM should be in all bank precharge
with CKE already high prior to writing into the extended
mode register. The mode register set command cycle
time (
operation to the EMRS(1). Mode register contents can
be changed using the same command and clock cycle
requirements during normal operation as long as all
banks are in precharge state.
A7
512-Mbit Double-Data-Rate-Two SDRAM
B
HYB18T512[400/800/160]A[C/F]–[3.7/5]
)
t
MRD
Rtt
A6
w
) must be satisfied to complete the write
A5
AL
A4
w
A3
Functional Description
09112003-SDM9-IQ3P
Rev. 1.13, 2004-05
Rtt
A2
w
DIC
A1
w
DLL
A0
w