HYB18T512160AC-37 INFINEON [Infineon Technologies AG], HYB18T512160AC-37 Datasheet - Page 48

• Manufacturer Part Number: HYB18T512160AC-37
• Description: 512-Mbit Double-Data-Rate-Two SDRAM
• Manufacturer: INFINEON [Infineon Technologies AG]

2.7
The Precharge Command is used to precharge or close
a bank that has been activated. The Precharge
Command is triggered when CS, RAS and WE are low
and CAS is high at the rising edge of the clock. The Pre-
Table 13
A10
LOW
LOW
LOW
LOW
HIGH
Note: The bank address assignment is the same for activating and precharging a specific bank.
2.7.1
The following rules apply as long as the
parameter - Internal Read to Precharge Command
delay time - is less or equal two clocks, which is the
case for operating frequencies less or equal 266 Mhz
(DDR2 400 and 533 speed sorts):
Minimum Read to Precharge command spacing to the
same bank = AL + BL/2 clocks. For the earliest possible
precharge, the Precharge command may be issued on
the rising edge which is “Additive Latency (AL) + BL/2
clocks” after a Read Command, as long as the
minimum
Figure 39
Data Sheet
C K , C K
C M D
D Q S ,
D Q S
D Q
t
RAS
P o s t C A S
R E A D A
T0
Precharge Command
Bank Selection for Precharge by Address Bits
Read Operation Followed by a Precharge
Read Operation Followed by Precharge Example 1:
RL = 4 (AL = 1, CL = 3), BL = 4,
timing is satisfied.
A L = 1
LOW
LOW
HIGH
HIGH
Don’t Care
BA0
T1
A L + B L /2 clks
N O P
> = tR A S
R L = 4
> = tR T P
C L = 3
T2
N O P
> = tR C
t
RTP
P re ch a rg e
T3
timing
BA1
LOW
HIGH
LOW
HIGH
Don’t Care
t
RTP
2 clocks
48
T4
N O P
Dout A0
tR P
charge Command can be used to precharge each bank
independently or all banks simultaneously. Three
address bits A10, BA0 and BA1 are used to define
which bank to precharge when the command is issued.
A new bank active command may be issued to the
same bank if the following two conditions are satisfied
simultaneously:
1. The RAS precharge time (
2. The RAS cycle time (
For operating frequencies higher than 266 MHz,
becomes > 2 clocks and one additional clock cycle has
to be added for the minimum Read to Precharge
command spacing, which now becomes AL + BL/2 + 1
clocks.
C L = 3
512-Mbit Double-Data-Rate-Two SDRAM
from the clock at which the precharge begins.
activation has been satisfied.
Dout A1
HYB18T512[400/800/160]A[C/F]–[3.7/5]
T5
N O P
Dout A2
Dout A3
Precharge Bank(s)
Bank 0 only
Bank 1 only
Bank 2 only
Bank 3 only
all banks
T6
B a n k A
A ctiva te
t
RC, min
t
T7
Functional Description
) from the previous bank
RP
N O P
09112003-SDM9-IQ3P
) has been satisfied
Rev. 1.13, 2004-05
T8
N O P
BR-P413
t
RTP