HYB18T512160AC-37 INFINEON [Infineon Technologies AG], HYB18T512160AC-37 Datasheet - Page 51

• Manufacturer Part Number: HYB18T512160AC-37
• Description: 512-Mbit Double-Data-Rate-Two SDRAM
• Manufacturer: INFINEON [Infineon Technologies AG]

2.7.2
Minimum Write to Precharge command spacing to the
same bank = WL + BL/2 +
must be satisfied from the completion of the last burst
write cycle until the Precharge command can be
issued. This delay is known as a write recovery time
(
Figure 44
Figure 45
Data Sheet
t
WR
C M D
C K , C K
D Q S ,
D Q S
D Q
C M D
C K , C K
D Q
) referenced from the completion of the burst write
D Q S ,
D Q S
W R IT E A
P o st C A S
W R IT E A
T0
P o s t C A S
T0
Write followed by Precharge
Write followed by Precharge Example 1: WL = (RL - 1) = 3, BL = 4,
Write followed by Precharge Example 2: WL = (RL - 1) = 4, BL = 4,
T1
T1
N O P
N O P
WL = 3
WL = 4
t
WR
. For write cycles, a delay
T2
T2
N O P
N O P
DIN A0 DIN A1 DIN A2 DIN A3
T3
T3
N O P
N O P
DIN A0 DIN A1 DIN A2 DIN A3
T4
T4
N O P
51
N O P
to the Precharge command. No Precharge command
should be issued prior to the
SDRAM does not support any burst interrupt by a
Precharge command.
parameter (see
value for
512-Mbit Double-Data-Rate-Two SDRAM
HYB18T512[400/800/160]A[C/F]–[3.7/5]
T5
T5
N O P
N O P
C o m p le tio n o f
th e B u rst W rite
t
WR
in the MRS.
Chapter
T6
T6
N O P
N O P
tW R
C o m p le tio n o f
th e B u rst W rite
t
WR
7) and is not the programmed
t
t
tW R
is an analog timing
WR
WR
T7
T7
N O P
t
N O P
= 3
= 3
WR
Functional Description
09112003-SDM9-IQ3P
delay, as DDR2
Rev. 1.13, 2004-05
P re ch a rg e
T9
P re ch a rg e
T8
A
A
BW-P4
BW-P3