HYB18T512160AC-37 INFINEON [Infineon Technologies AG], HYB18T512160AC-37 Datasheet - Page 37

• Manufacturer Part Number: HYB18T512160AC-37
• Description: 512-Mbit Double-Data-Rate-Two SDRAM
• Manufacturer: INFINEON [Infineon Technologies AG]

beginning with the column address supplied to the
device during the Read or Write Command (CA[9:0] &
CA11).
A new burst access must not interrupt the previous 4 bit
burst operation in case of BL = 4 setting. Therefore the
Figure 18
2.6.1
Posted CAS operation is supported to make command
and data bus efficient for sustainable bandwidths in
DDR2 SDRAM. In this operation, the DDR2 SDRAM
allows a Read or Write command to be issued
immediately after the RAS bank activate command (or
any time during the RAS to CAS delay time,
period). The command is held for the time of the
Additive Latency (AL) before it is issued inside the
device. The Read Latency (RL) is the sum of AL and
Figure 19
Data Sheet
DQS,
DQS
CMD
CK, CK
DQ
READ A
T
0
Read Burst Timing Example: (CL = 3, AL = 0, RL = 3, BL = 4)
Posted CAS
Activate to Read Timing Example : Read followed by a write to the same bank, Activate to
Read delay <
CK, CK
DQS,
DQS
CMD
DQ
T
1
NOP
tCCD
Activate
Bank A
0
t
Bank A
RCDmin
READ B
Read
1
T
2
tRCD
AL = 2
: AL = 2 and CL = 3, RL = (AL + CL) = 5, WL = (RL -1) = 4, BL = 4
2
RL = AL + CL = 5
T
3
NOP
Dout A0
tCCD
3
t
RCD
Dout A1
4
READ C
T
4
CL = 3
Dout A2
Bank A
5
Write
37
Dout A3
minimum CAS to CAS delay (
clocks for read or write cycles.
For 8 bit burst operation (BL = 8) the minimum CAS to
CAS delay (
Burst interruption is allowed with 8 bit burst operation.
For details see
the CAS latency (CL). Therefore if a user chooses to
issue a Read/Write command before the
AL greater than 0 must be written into the EMRS(1).
The Write Latency (WL) is always defined as RL - 1
(Read Latency -1) where Read Latency is defined as
the sum of Additive Latency plus CAS latency
(RL=AL+CL). If a user chooses to issue a Read
command after the
also defined as RL = AL + CL.
T
5
NOP
Dout B0
512-Mbit Double-Data-Rate-Two SDRAM
6
Dout0
WL = RL -1 = 4
HYB18T512[400/800/160]A[C/F]–[3.7/5]
Dout B1
Dout1
7
Dout2
T
6
NOP
t
CCD
Dout B2
Dout3
Chapter
) is 4 clocks for read or write cycles.
8
Dout B3
t
RCD, min
T
7
NOP
Din0
9
Dout C0
2.6.6.
Din1
period, the Read Latency is
Dout C1
10
Din2
t
Functional Description
CCD
09112003-SDM9-IQ3P
NOP
Din3
T12
Dout C2
) is a minimum of 2
11
Rev. 1.13, 2004-05
PostCAS1
Dout C3
RB
NOP
t
RCD, min
, then