NAND04G-B2D NUMONYX [Numonyx B.V], NAND04G-B2D Datasheet - Page 35

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NAND04G-B2D

Manufacturer Part Number
NAND04G-B2D
Description
4 Gbit, 8 Gbit, 2112 byte/1056 word page multiplane architecture, 1.8 V or 3 V, NAND Flash memories
Manufacturer
NUMONYX [Numonyx B.V]
Datasheet
NAND04G-B2D, NAND08G-BxC
6.11.5
Table 14.
1. Only valid for cache operations.
6.12
6.13
SR4, SR3,
SR2, SR1
SR7
SR6
SR5
SR0
Bit
SR4, SR3, SR2 and SR1 are reserved
Status Register bits
Read status enhanced
In NAND Flash devices with multiplane architecture, it is possible to independently read the
Status Register of a single plane using the Read Status Enhanced command. If the Error bit
of the Status Register, SR0, reports an error during or after a multiplane operation, the Read
Status Enhanced command is used to know which of the two planes contains the page that
failed the operation. Three address cycles are required to address the selected block and
page (A18-0).
The output of the Read Status Enhanced command has the same coding as the Read
Status command. See
enhanced waveform.
Read EDC Status Register
The devices contain an EDC Status Register, which provides information on the errors that
occurred during the read cycles of the copy back and multiplane copy back operations. In
the case of multiplane copy back program, it is not possible to distinguish which of the two
read operations caused the error.
The EDCS Status Register is read by issuing the Read EDC Status Register command.
After issuing the Read EDC Status Register command, a read cycle outputs the content of
the EDC Status Register to the I/O pins on the falling edge of Chip Enable or Read Enable
signals, whichever occurs last. The operation is similar to Read Status Register command.
Table 15: EDC Status Register bits
Figure 30
Program/Erase/Read
Program/Erase/Read
Write protection
for a description of Read EDC Status Register waveforms.
Generic error
Controller
Controller
Reserved
Name
(1)
Table 14
for a full description and
Logic level
‘don’t care’
summarizes the EDC Status Register bits. See
‘1’
‘0’
'1'
'0'
'1'
'0'
'1'
'0'
Not protected
Protected
P/E/R Controller inactive, device ready
P/E/R Controller active, device busy
P/E/R Controller inactive, device ready
P/E/R Controller active, device busy
Error – operation failed
No error – operation successful
Figure 31
Definition
for the read status
Device operations
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