NAND04G-B2D NUMONYX [Numonyx B.V], NAND04G-B2D Datasheet - Page 28

• Manufacturer Part Number: NAND04G-B2D
• Description: 4 Gbit, 8 Gbit, 2112 byte/1056 word page multiplane architecture, 1.8 V or 3 V, NAND Flash memories
• Manufacturer: NUMONYX [Numonyx B.V]

Device operations
6.4
Figure 13. Multiplane page program waveform
1. The 81h setup code is also accepted for backward compatibility.
28/69
RB
I/O
Page Program
Setup Code
80h
Multiplane page program
The devices support multiplane page program, which enables the programming of two
pages in parallel, one in each plane.
A multiplane page program operation requires the following two steps:
1.
2.
As for standard page program operation, the device supports random data input during both
data loading phases.
Once the multiplane page program operation has started, that is during a delay of t
Status Register can be read using the Read Status Register command.
Once the multiplane page program operation has completed, the P/E/R Controller bit SR6 is
set to ‘1’ and the Ready/Busy signal goes High.
If the multiplane page program fails, an error is signaled on bit SR0 of the Status Register.
To know which page of the two planes failed, the Read Status Enhanced command must be
issued twice, once for each plane (see
Figure 13
Address Inputs
The first step serially loads up to two pages of data (4224 bytes) into the data buffer. It
requires:
–
–
–
–
The 2nd step programs in parallel the two pages of data loaded into the data buffer into
the appropriate memory pages. It is started by issuing a the Program Confirm
command.
A18=0
One clock cycle to set up the Page Program command (see
Sequential
5 bus write cycles to input the first page address and data. The address of the first
page must be within the first plane (A18 = 0).
One bus write cycle to issue the Page Program Confirm code. After this, the
device is busy for a time of t
When the device returns to the ready state (Ready/Busy High), a multiplane page
program setup code must be issued, followed by the 2nd page address (5 write
cycles) and data. The address of the 2nd page must be within the second plane
(A18 = 1).
provides a description of multiplane page program waveforms.
Data Input
input).
tIPBSY
Confirm
Code
11h
Busy
Multiplane Page
Program Setup
80h (1)
code
IPBSY.
Section
Address Inputs
A18=1
6.12).
Data Input
NAND04G-B2D, NAND08G-BxC
(Program Busy time)
tBLBH2
Confirm
Code
10h
Section 6.3.1:
Busy
Read Status Register
70h
ai13171b
IPBSY
SR0
, the