NAND04G-B2D NUMONYX [Numonyx B.V], NAND04G-B2D Datasheet - Page 26

• Manufacturer Part Number: NAND04G-B2D
• Description: 4 Gbit, 8 Gbit, 2112 byte/1056 word page multiplane architecture, 1.8 V or 3 V, NAND Flash memories
• Manufacturer: NUMONYX [Numonyx B.V]

Device operations
6.3
6.3.1
6.3.2
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Page program
The page program operation is the standard operation to program data to the memory array.
Generally, the page is programmed sequentially, however, the device does support random
input within a page.
It is recommended to address pages sequentially within a given block.
The memory array is programmed by page, however, partial page programming is allowed
where any number of bytes (1 to 2112) or words (1 to 1056) can be programmed.
The maximum number of consecutive, partial-page program operations allowed in the same
page is four. After exceeding four operations a Block Erase command must be issued before
any further program operations can take place in that page.
Sequential input
To input data sequentially the addresses must be sequential and remain in one block.
For sequential input each page program operation consists of the following five steps :
1.
2.
3.
4.
5.
See
Random data input in page
During a sequential input operation, the next sequential address to be programmed can be
replaced by a random address by issuing a Random Data Input command. The following
two steps are required to issue the command:
1.
2.
Random data input can be repeated as often as required in any given page.
Once the program operation has started, the Status Register can be read using the Read
Status Register command. During program operations the Status Register only flags errors
for bits set to '1' that have not been successfully programmed to '0'.
During the program operation, only the Read Status Register and Reset commands are
accepted; all other commands are ignored.
Once the program operation has completed, the P/E/R Controller bit SR6 is set to ‘1’ and
the Ready/Busy signal goes High.
The device remains in Read Status Register mode until another valid command is written to
the command interface.
Figure 11: Page program operation
One bus cycle is required to set up the Page Program (sequential input) command (see
Table 10:
Five bus cycles are then required to input the program address (refer to
Address insertion (x8 devices)
The data is then loaded into the Data Registers.
One bus cycle is required to issue the Page Program Confirm command to start the
P/E/R Controller. The P/E/R only starts if the data has been loaded in step
the P/E/R Controller then programs the data into the array.
One bus cycle is required to set up the Random Data Input command (see
Commands).
Two bus cycles are then required to input the new column address (refer to
Address insertion (x8
Commands).
devices)).
and
Table 7: Address insertion (x16
for more information.
NAND04G-B2D, NAND08G-BxC
devices)).
Table 6:
3.
Table 10:
Table 6: