HD64F7050 RENESAS [Renesas Technology Corp], HD64F7050 Datasheet - Page 667
HD64F7050
Manufacturer Part Number
HD64F7050
Description
32-Bit RISC Microcomputer SuperH RISC engine Family/
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
1.HD64F7050.pdf
(841 pages)
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21.4
21.4.1
To enter the standby mode, set the SBY bit to 1 in SBYCR, then execute the SLEEP instruction.
The LSI moves from the program execution state to the standby mode. In the standby mode,
power consumption is greatly reduced by halting not only the CPU, but the clock and on-chip
peripheral modules as well. CPU register contents and on-chip RAM data are held as long as the
prescribed voltages are applied (when the RAME bit in SYSCR is 0). The register contents of
some on-chip peripheral modules are initialized, but some are not (table 21.4). The I/O port status
can be selected as held or high impedance by the port high impedance bit (HIZ) of the SBYCR.
For pin status other than for the I/O port, refer to Appendix B, Pin States.
Oscillator
HSTBY
RES
Transition to Software Standby Mode
Software Standby Mode
Figure 21.1 Hardware Standby Mode Timing
RES pulse
width t
RESW
Rev. 5.00 Jan 06, 2006 page 647 of 818
Section 21 Power-Down State
Oscillation
stabilization
time
REJ09B0273-0500
Reset
exception
handling
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