HD64F7050 RENESAS [Renesas Technology Corp], HD64F7050 Datasheet - Page 161

• Manufacturer Part Number: HD64F7050
• Description: 32-Bit RISC Microcomputer SuperH RISC engine Family/
• Manufacturer: RENESAS [Renesas Technology Corp]

9.2.2
DMA destination address registers 0–3 (DAR0–DAR3) are 32-bit read/write registers that specify
the destination address of a DMA transfer. These registers have a count function, and during a
DMA transfer, they indicate the next destination address. In single-address mode, DAR values are
ignored when a device with DACK has been specified as the transfer destination.
Specify a 16-bit boundary when performing 16-bit data transfers, and a 32-bit boundary when
performing 32-bit data transfers. Operation cannot be guaranteed if any other addresses are set.
The value after power-on resets and in standby mode is undefined.
Initial value:
Initial value:
Initial value:
Initial value:
DMA Destination Address Registers 0–3 (DAR0–DAR3)
R/W:
R/W:
R/W:
R/W:
Bit:
Bit:
Bit:
Bit:
R/W
R/W
R/W
R/W
31
23
31
23
—
—
—
—
R/W
R/W
R/W
R/W
30
22
30
22
—
—
—
—
R/W
R/W
R/W
R/W
29
21
29
21
—
—
—
—
Section 9 Direct Memory Access Controller (DMAC)
R/W
R/W
28
28
—
…
…
…
…
—
…
…
…
…
Rev. 5.00 Jan 06, 2006 page 141 of 818
R/W
R/W
27
27
—
…
…
…
…
—
…
…
…
…
R/W
R/W
R/W
R/W
26
26
—
—
—
—
2
2
REJ09B0273-0500
R/W
R/W
R/W
R/W
25
25
—
—
—
—
1
1
R/W
R/W
R/W
R/W
24
24
—
—
—
—
0
0