HD64F7050 RENESAS [Renesas Technology Corp], HD64F7050 Datasheet - Page 448

• Manufacturer Part Number: HD64F7050
• Description: 32-Bit RISC Microcomputer SuperH RISC engine Family/
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 13 Serial Communication Interface (SCI)
The receive margin in the asynchronous mode can therefore be expressed as:
From the equation above, if F = 0 and D = 0.5 the receive margin is 46.875%:
This is a theoretical value. A reasonable margin to allow in system designs is 20–30%.
Rev. 5.00 Jan 06, 2006 page 428 of 818
REJ09B0273-0500
Synchronization
sampling timing
sampling timing
data (RxD)
base clock
M = 0.5
M : Receive margin (%)
N : Ratio of clock frequency to bit rate (N = 16)
D : Clock duty cycle (D = 0–1.0)
L : Frame length (L = 9–12)
F : Absolute deviation of clock frequency
D = 0.5, F = 0
M = (0.5 – 1/(2
Receive
Internal
Figure 13.23 Receive Data Sampling Timing in Asynchronous Mode
= 46.875%
Data
(
0
2N
1
8 clocks
Start bit
)
16))
(L
16 clocks
0.5) F
100%
7 8
–7.5 clocks
D
N
0.5
15 0
(1
+7.5 clocks
F)
100%
D0
7 8
15 0
D1
5