HD64F7050 RENESAS [Renesas Technology Corp], HD64F7050 Datasheet - Page 356
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HD64F7050
Manufacturer Part Number
HD64F7050
Description
32-Bit RISC Microcomputer SuperH RISC engine Family/
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
1.HD64F7050.pdf
(841 pages)
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Section 10 Advanced Timer Unit (ATU)
Halting of a Down-Counter by the CPU: A down-counter (DCNT) can be halted by writing
H'0000 to it. The CPU cannot write 0 directly to the down-count start register (DSTR); instead, by
setting DCNT to H'0000, the corresponding DSTR bit is cleared to 0 and the count is stopped.
However, the OSF bit in the timer status register (TSR) is set when DCNT underflows.
Note that when H'0000 is written to DCNT, the corresponding DSTR bit is not cleared to 0
immediately; it is cleared to 0, and the down-counter is stopped, when underflow occurs following
the H'0000 write.
The timing in this case is shown in figure 10.60
Rev. 5.00 Jan 06, 2006 page 336 of 818
REJ09B0273-0500
Internal write signal
DCNT input clock
(one-shot pulse)
Port output
Figure 10.60 Halting of a Down-Counter by the CPU
DCNT
DSTR
TSR
CK
H'0000
written
to DCNT
N
H'0000
H'0000
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