HD64F7050 RENESAS [Renesas Technology Corp], HD64F7050 Datasheet - Page 146
HD64F7050
Manufacturer Part Number
HD64F7050
Description
32-Bit RISC Microcomputer SuperH RISC engine Family/
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
1.HD64F7050.pdf
(841 pages)
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Section 8 Bus State Controller (BSC)
When the wait is specified by software using WCR, the wait input WAIT signal from outside is
sampled. Figure 8.5 shows the WAIT signal sampling. The WAIT signal is sampled at the clock
rise one cycle before the clock rise when T
a WCR setting of 1 state or more when extending CS assertion, and 2 states or more otherwise.
Rev. 5.00 Jan 06, 2006 page 126 of 818
REJ09B0273-0500
Figure 8.5 Wait State Timing of Ordinary Space Access (Wait States from Software Wait 2
Read
Write
Address
WAIT
WRx
Data
Data
CSn
RD
CK
T
1
State + WAIT
T
W
w
state shifts to T
WAIT
WAIT
WAIT Signal)
T
W
2
state. When using external waits, use
T
W
0
T
2
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