HD64F7050 RENESAS [Renesas Technology Corp], HD64F7050 Datasheet - Page 616
HD64F7050
Manufacturer Part Number
HD64F7050
Description
32-Bit RISC Microcomputer SuperH RISC engine Family/
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
1.HD64F7050.pdf
(841 pages)
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Section 19 ROM (256 kB Version)
Bit 6—Software Write Enable Bit (SWE): Enables or disables the flash memory. This bit should
be set when setting bits 5 to 0, FLMCR2 bits 5 to 0, EBR1 bits 3 to 0, and EBR2 bits 7 to 0.
Bit 6:
SWE
0
1
Bit 5—Erase Setup Bit 1 (ESU1): Prepares for a transition to erase mode (applicable addresses:
H'00000 to H'1FFFFF). Do not set the SWE, PSU1, EV1, PV1, E1, or P1 bit at the same time.
Bit 5:
ESU1
0
1
Bit 4—Program Setup Bit 1 (PSU1): Prepares for a transition to program mode (applicable
addresses: H'00000 to H'1FFFFF). Do not set the SWE, ESU1, EV1, PV1, E1, or P1 bit at the
same time.
Bit 4:
PSU1
0
1
Rev. 5.00 Jan 06, 2006 page 596 of 818
REJ09B0273-0500
Description
Writes disabled
Writes enabled
[Setting condition]
When FWE = 1
Description
Erase setup cleared
Erase setup
[Setting condition]
When FWE = 1 and SWE = 1
Description
Program setup cleared
Program setup
[Setting condition]
When FWE = 1 and SWE = 1
(Initial value)
(Initial value)
(Initial value)
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