PSB7238 SIEMENS [Siemens Semiconductor Group], PSB7238 Datasheet - Page 54

• Manufacturer Part Number: PSB7238
• Description: Joint Audio Decoder-Encoder - Multimode
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

PSB 7238
Functional Blocks
After reset (RRES) when starting the receiver (RAC = 1), the reset status data of HRW
and HRR is ignored by the receiver, i.e. the contents of HRW1/2 and HRR1/2 are not
forwarded to the HDLC receiver, but only the data received from the line. The same
applies to the interrupts: A BFHR1/2 interrupt is only generated after the first 1, 2 or
4 bytes of line data are available in the HRR1/2 register. Due to this pipeline, a latency
occurs in the HDLC/transparent serial data reception, see section below.
The start of the reception can be in the same frame (w.r.t. frame sync signal on the
chosen line) as the setting of RAC = 1 since the time-slot count logic works
independently of RAC.
In transparent mode (TMO = 1) the reception is only started at the beginning of the
time-slot (time-slot aligned). If RAC is set to ‘1’ during the selected time-slot, the receiver
waits for the beginning of the time-slot in the next frame.
Receiver in LMOD(1:0) = 00
The same applies for LMOD = 00, except the pre-processing is not available. The data
from the bit-reversal unit is bypassed to the HDLC receiver. In addition, the loading of
HRR1/2, HRW1/2 and the generation of the interrupt BFHR1/2 is done like in the other
LMODs for observation of the data stream by the DSP or host only. Thus, the
LMOD = 00 is identical with LMOD = 01, except pre-processing is not available and the
receiver latency after reset is shortened, see section below.
Transmitter in LMOD(1:0) = 01, 10, 11
Similarly, in the transmit direction, after 1, 2 or 4 bytes (programmable) are shifted out of
the shift register, the contents of the HXW1/2 write register accessible from DSP
(if HHX1/2 = 0) or host (if HHX1/2 = 1) are loaded into the transmitter shift register. In the
same cycle 1, 2 or 4 bytes are loaded from the HDLC transmitter output into the HXR1/2
read register, physically separate for DSP and host. In the next cycle the data from
HXR1/2 is as a default loaded into HXW1/2 and a maskable interrupt status is generated
to the DSP and host. The interrupt status is generated to both DSP and host,
independent of the setting of HAH1/2. If the data in HXR1/2 is to be post-processed, the
HXW1/2 register can be overwritten by the DSP or host before the next 1, 2 or 4 bytes
(programmable) have been shifted out of the shift register.
After reset (XRES), the reset status data of HXR1/2 and HXW1/2 is ignored by the
transmitter, i.e. the contents of HXR1/2 and HXW1/2 are not transmitted to the line, but
only the data from the HDLC transmitter. In the first cycle after the transmitter has been
activated (XAC = 1), the data from the HDLC transmitter is immediately passed to the
HXR1/2 register for post-processing. The line-transmission is not yet started! In the first
cycle after the DSP or host (programmable via HHX1/2) has written the HXW1/2 register
with the post-processed value, this value is passed through the bit-reversal unit into the
shift register and the transmission is started as soon as the next beginning of the
selected time-slot is detected.
Semiconductor Group
54
Data Sheet 1998-07-01