PSB7238 SIEMENS [Siemens Semiconductor Group], PSB7238 Datasheet - Page 123

• Manufacturer Part Number: PSB7238
• Description: Joint Audio Decoder-Encoder - Multimode
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

CCR1
RCS0
RSCO
RFDIS
XCS0
Channel Configuration Register 1 CCR1
Semiconductor Group
RCS0
Together with RCS2 and RCS1 in TSAR, determines the clock shift relative
to the frame synchronization signal. A clock shift of 0 … 7 is programmable.
Receive Time-Slot Continuous
When RSCO is equal to one, the time-slot capacity (normally given by
register RCCR, between 1 and 256 bits) is “infinity”. This means that the
time-slot will be always “active” so that data can be permanently received if
RAC = 1.
If RFDIS = 0, and if the time-slot count logic has been reset (by issuing
RRES while RAC = 0), time-slot logic can start operation and thus “activate”
a time-slot only after the first frame sync pulse is detected (i.e. on FSC, RFS,
or TFS, whichever has been selected). The time-slot offset register
TSAR + bit RCS0 mark the instant when the “infinite” time-slot will be
activated after the first frame sync pulse has occurred. If RFDIS = 1,
reception can start immediately, without the necessity to wait for the first
frame sync pulse.
When RFDIS is ‘1’, the time-slot generation logic disregards frame syncs. In
particular, if RFDIS = 1, receive time-slot is immediately considered as
permanently “active”, and remains activated as long as this condition
prevails, independent of RSCO.
Transmit Clock Shift 0
Together with XCS2 and XCS1 in TSAX, determines the clock shift relative
to the frame synchronization signal. A clock shift of 0 … 7 is programmable.
Receive Clock Shift 0
Receive Frame Sync Disregard
Bit 7
RSCO
RFDIS
XCS0
123
TSCO
Read/Write
XFDIS
Register Description
Data Sheet 1998-07-01
Address 27
PSB 7238
Bit 0
H