PSB7238 SIEMENS [Siemens Semiconductor Group], PSB7238 Datasheet - Page 45

• Manufacturer Part Number: PSB7238
• Description: Joint Audio Decoder-Encoder - Multimode
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

CM1 = 0
CM1 = 1
The block diagram of the clock circuitry is shown in Figure 16.
Figure 16
4
4.1
Clocking Modes
The clock generator including PLL generates the internal master clock derived from an
input clock (or crystal) on pins XTAL(1:2).
Because of integrated decoupling capacitors, DC components of the input frequency on
XTAL(1:2) are filtered out. Consequently, for a crystal input (nearly a sinusoid), an
internal clock of nearly 50% duty cycle results.
The different clock modes available in the PSB 7238 are as follows:
For the clock generation unit (oscillator and PLL) a separate supply voltage pin (
and
Semiconductor Group
VD DA, VS S A
P owe r s upply)
V
(Se pa r a te
DDAP
X TAL1
X TAL2
CM1
Functional Blocks
PLL and Baud Rate Generator
and a separate ground pin (
Os cillator
PLL is activated by firmware after reset. The internal clock circuitry
generates a frequency 4.5 times the input on XTAL(1,2). The internal
frequency required is 34.56 MHz and is obtained by providing a
frequency of 7.68 MHz on XTAL1 input.
PLL inactive. The internal frequency is directly input via XTAL(1,2).
When using a crystal, a 34.56 MHz crystal swinging at its basic
harmonic has to be connected to XTAL(1,2).
F o r C M1 = 0 (input 7 , 6 8 MHz)
/2
P LL/Clo c k ge n erator c irc uit
x 1 8
CM1
DIV
7 ,6 8 MHz
V
SSA
/2
45
and
3 4. 56 MHz
V
SSAP
C M1
0
1
M
U
X
are provided.
DIV
INT0
INT1
19
C LKO
CKOS
CKOEN
OR
Data Sheet 1998-07-01
CKOBR
CKOEN
Functional Blocks
PU
1 => s e t P U
T3 EN
T3
AND
1 4
T3 inte rrupt s tatus
PSB 7238
DSP
/25 6
/ T3
D S P
clo ck
V
DDA