PSB7238 SIEMENS [Siemens Semiconductor Group], PSB7238 Datasheet - Page 38

• Manufacturer Part Number: PSB7238
• Description: Joint Audio Decoder-Encoder - Multimode
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

PSB 7238
Interfaces and Memory Organization
Interrupt from DSP to Host
For a soft interrupt from the DSP to the host, the procedure is identical. In this case, the
soft interrupt is a maskable interrupt on line INT. The interrupt vector is written by the
DSP in address 3058
(IND). Simultaneously, the Interrupt DSP Busy bit INDB (address
H
58
, writable by host) is set to ‘1’. Having recognized an IND interrupt status, the host
H
reads address 58
(IND), which automatically resets the DINT interrupt status bit in the
H
Host Interrupt Status Register for INT (address 75
). The INDB bit can be written by the
H
host again to ‘0’ to indicate that it is ready to accept a new interrupt from the DSP. The
16-bit control register located at 60/61
(3060/3061
) may contain additional information
H
H
for the host to read after an IND interrupt. Please refer to the specific interface
procedures for details.
Registers for Accessing the External Memory
In normal operation, the program bus of the DSP is connected via the external memory
interface to the external memory bus so that instructions are fetched from an external
memory when an address between 8000
and FFFF
is hit, if EA = “High”. If EA = “Low”,
H
H
the whole address range is for off-chip programs.
If the bit LDMEM (see description of Configuration and Control Registers, Chapter 4) is
set to ‘1’ and bit DACC is ‘0’ (see description of Configuration and Control Registers,
Chapter 5.3), the external memory interface address and data buses are connected to
the outputs of registers address low/high (at host address 44/45
) and data low/high (at
H
host address 46/47
), respectively. This feature can be used to down-load programs into
H
a memory connected to the PSB 7238.
When a write access to the data high register (address 47
) is detected, this activates
H
the external memory interface write signal CWR for the duration of the host WR signal
(independent of any possible wait states in NRW(3:0)).
Thus the host writes one word of data into an external memory by effecting the following
write operations:
Write Address Low + High
Write Data Low
Write Data High (operation is carried out during this write cycle).
When LDMEM is ‘1’, the CPS signal is permanently active.
Note: When LDMEM is ‘0’, the CPS signal is activated when a read access - program
fetch - is performed on the external memory interface.
Semiconductor Group
38
Data Sheet 1998-07-01