MC68HC912D60A MOTOROLA [Motorola, Inc], MC68HC912D60A Datasheet - Page 35

• Manufacturer Part Number: MC68HC912D60A
• Description: Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

2.6 Indexed Addressing Modes
MC68HC912D60A — Rev 3.0
MOTOROLA
rr0nnnnn
111rr0zs
111rr011
rr1pnnnn
111rr1aa
111rr111
Code (xb)
Postbyte
The CPU12 indexed modes reduce execution time and eliminate code
size penalties for using the Y index register. CPU12 indexed addressing
uses a postbyte plus zero, one, or two extension bytes after the
instruction opcode. The postbyte and extensions do the following tasks:
,r
n,r
[n,r]
n,–r n,+r
A,r
[D,r]
•
•
•
•
Freescale Semiconductor, Inc.
n,r
–n,r
–n,r
n,r– n,r+
B,r
D,r
Source
Syntax
Code
For More Information On This Product,
Specify which index register is used.
Determine whether a value in an accumulator is used as an offset.
Enable automatic pre- or post-increment or decrement
Specify use of 5-bit, 9-bit, or 16-bit signed offsets.
Table 2-2. Summary of Indexed Operations
Go to: www.freescale.com
5-bit constant offset n = –16 to +15
Constant offset (9- or 16-bit signed)
16-bit offset indexed-indirect
Auto pre-decrement/increment or Auto post-
Accumulator offset (unsigned 8-bit or 16-bit)
Accumulator D offset indexed-indirect
Central Processing Unit
rr can specify X, Y, SP, or PC
z-0 = 9-bit with sign in LSB of postbyte(s)
1 = 16-bit
if z = s = 1, 16-bit offset indexed-indirect (see below)
rr can specify X, Y, SP, or PC
rr can specify X, Y, SP, or PC
decrement/increment;
p = pre-(0) or post-(1), n = –8 to –1, +1 to +8
rr can specify X, Y, or SP (PC not a valid choice)
aa-00 = A
01 = B
10 = D (16-bit)
11 = see accumulator D offset indexed-indirect
rr can specify X, Y, SP, or PC
rr can specify X, Y, SP, or PC
Comments
Indexed Addressing Modes
Central Processing Unit
Technical Data
35