MC68HC912D60A MOTOROLA [Motorola, Inc], MC68HC912D60A Datasheet - Page 274
MC68HC912D60A
Manufacturer Part Number
MC68HC912D60A
Description
Microcontrollers
Manufacturer
MOTOROLA [Motorola, Inc]
Datasheet
1.MC68HC912D60A.pdf
(460 pages)
- Current page: 274 of 460
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Multiple Serial Interface
SC0SR2 — SCI Status Register 2
Technical Data
274
1. See
RESET:
Motorola Interconnect Bus
SCSWAI
Bit 7
0
MIE
6
0
PF — Parity Error Flag
Read anytime. Write has no meaning or effect.
SCSWAI — Serial Communications Interface Stop in WAIT Mode
RAF — Receiver Active Flag
(1)
Indicates if received data’s parity matches parity bit. This feature is
active only when parity is enabled. The type of parity tested for is
determined by the PT (parity type) bit in SCxCR1.
for descriptions of these bits.
This bit is controlled by the receiver front end. It is set during the RT1
time period of the start bit search. It is cleared when an idle state is
detected or when the receiver circuitry detects a false start bit
(generally due to noise or baud rate mismatch).
If enabled with RIE = 1, RAF set generates an interrupt when
VDDPLL is high.
Freescale Semiconductor, Inc.
For More Information On This Product,
0 = Parity correct
1 = Incorrect parity detected
0 = SCI clock operates normally.
1 = Halt SCI clock generation when in WAIT mode.
0 = A character is not being received
1 = A character is being received
MDL1
5
0
(1)
Go to: www.freescale.com
Multiple Serial Interface
MDL0
4
0
(1)
3
0
0
2
0
0
MC68HC912D60A — Rev 3.0
1
0
0
Bit 0
RAF
0
$00C5/$00CD
MOTOROLA
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