MC68HC912D60A MOTOROLA [Motorola, Inc], MC68HC912D60A Datasheet - Page 160
MC68HC912D60A
Manufacturer Part Number
MC68HC912D60A
Description
Microcontrollers
Manufacturer
MOTOROLA [Motorola, Inc]
Datasheet
1.MC68HC912D60A.pdf
(460 pages)
- Current page: 160 of 460
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Clock Functions
CLKSEL — Clock Generator Clock select Register
Technical Data
160
RESET:
Bit 7
0
0
BCSP
6
0
Read and write anytime. Exceptions are listed below for each bit.
BCSP — Bus Clock Select PLL
BCSS — Bus Clock Select Slow
MCS — Module Clock Select
BCSP and BCSS bits determine the clock used by the main system
including the CPU and buses.
Cannot be set when PLLON = 0. In limp-home mode, the output of
BCSP is forced to 1, but the BCSP bit reads the latched value.
This bit has no effect when BCSP is set.
This bit determines the clock used by the ECT module and the baud
rate generators of the SCIs. In limp-home mode, the output of MCS is
forced to 0, but the MCS bit reads the latched value.
Freescale Semiconductor, Inc.
For More Information On This Product,
0 = SYSCLK is derived from the crystal clock or from SLWCLK.
1 = SYSCLK source is the PLL.
0 = SYSCLK is derived from the crystal clock EXTALi.
1 = SYSCLK source is the Slow clock SLWCLK.
0 = M clock is the same as PCLK.
1 = M clock is derived from Slow clock SLWCLK.
BCSS
5
0
Go to: www.freescale.com
Clock Functions
4
0
0
3
0
0
MCS
2
0
MC68HC912D60A — Rev 3.0
1
0
0
Bit 0
0
0
MOTOROLA
$003D
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