MC68HC912D60A MOTOROLA [Motorola, Inc], MC68HC912D60A Datasheet - Page 251
MC68HC912D60A
Manufacturer Part Number
MC68HC912D60A
Description
Microcontrollers
Manufacturer
MOTOROLA [Motorola, Inc]
Datasheet
1.MC68HC912D60A.pdf
(460 pages)
- Current page: 251 of 460
- Download datasheet (4Mb)
DLYCT — Delay Counter Control Register
ICOVW — Input Control Overwrite Register
MC68HC912D60A — Rev 3.0
MOTOROLA
RESET:
RESET:
NOVW7
BIT 7
BIT 7
0
0
0
NOVW6
6
0
6
0
0
Read: any time
Write: any time
If enabled, after detection of a valid edge on input capture pin, the delay
counter counts the pre-selected number of M clock (module clock)
cycles, then it will generate a pulse on its output. The pulse is generated
only if the level of input signal, after the preset delay, is the opposite of
the level before the transition.This will avoid reaction to narrow input
pulses.
After counting, the counter will be cleared automatically.
Delay between two active edges of the input signal period should be
longer than the selected counter delay.
DLYx — Delay Counter Select
Read: any time
Write: any time
Freescale Semiconductor, Inc.
For More Information On This Product,
NOVW5
5
0
5
0
0
Go to: www.freescale.com
Enhanced Capture Timer
NOVW4
4
0
4
0
0
DLY1
0
0
1
1
NOVW3
DLY0
3
0
3
0
0
0
1
0
1
NOVW2
Disabled (bypassed)
256 M clock cycles
512 M clock cycles
1024 M clock cycles
2
0
2
0
0
Delay
NOVW1
DLY1
1
0
1
0
Enhanced Capture Timer
NOVW0
DLY0
BIT 0
BIT 0
0
0
Timer Registers
Technical Data
$00AA
$00A9
251
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