MC68HC908AB32 MOTOROLA [Motorola, Inc], MC68HC908AB32 Datasheet - Page 307

no-image

MC68HC908AB32

Manufacturer Part Number
MC68HC908AB32
Description
HCMOS Microcontroller Unit
Manufacturer
MOTOROLA [Motorola, Inc]
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC68HC908AB32CFU
Manufacturer:
MOTOROLA
Quantity:
1 372
Part Number:
MC68HC908AB32CFU
Manufacturer:
MC
Quantity:
852
Part Number:
MC68HC908AB32CFU
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC68HC908AB32CFU
Manufacturer:
MOT
Quantity:
39
Part Number:
MC68HC908AB32CFU
Manufacturer:
FRE/MOT
Quantity:
20 000
Part Number:
MC68HC908AB32CFUE
Manufacturer:
ATMEL
Quantity:
1 001
Part Number:
MC68HC908AB32CFUE
Manufacturer:
FREE
Quantity:
6
Part Number:
MC68HC908AB32MPB
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
MC68HC908AB32
MOTOROLA
NOTE:
Rev. 1.0
ERRIE — Error Interrupt Enable Bit
OVRF — Overflow Bit
MODF — Mode Fault Bit
SPTE — SPI Transmitter Empty Bit
Do not write to the SPI data register unless the SPTE bit is high.
This read/write bit enables the MODF and OVRF bits to generate
CPU interrupt requests. Reset clears the ERRIE bit.
This clearable, read-only flag is set if software does not read the byte
in the receive data register before the next full byte enters the shift
register. In an overflow condition, the byte already in the receive data
register is unaffected, and the byte that shifted in last is lost. Clear the
OVRF bit by reading the SPI status and control register with OVRF set
and then reading the receive data register. Reset clears the OVRF bit.
This clearable, read-only flag is set in a slave SPI if the SS pin goes
high during a transmission with the MODFEN bit set. In a master SPI,
the MODF flag is set if the SS pin goes low at any time with the
MODFEN bit set. Clear the MODF bit by reading the SPI status and
control register (SPSCR) with MODF set and then writing to the SPI
control register (SPCR). Reset clears the MODF bit.
This clearable, read-only flag is set each time the transmit data
register transfers a byte into the shift register. SPTE generates an
SPTE CPU interrupt request if the SPTIE bit in the SPI control register
is set also.
During an SPTE CPU interrupt, the CPU clears the SPTE bit by
writing to the transmit data register.
Reset sets the SPTE bit.
Freescale Semiconductor, Inc.
For More Information On This Product,
1 = MODF and OVRF can generate CPU interrupt requests
0 = MODF and OVRF cannot generate CPU interrupt requests
1 = Overflow
0 = No overflow
1 = SS pin at inappropriate logic level
0 = SS pin at appropriate logic level
1 = Transmit data register empty
0 = Transmit data register not empty
Serial Peripheral Interface Module (SPI)
Go to: www.freescale.com
Serial Peripheral Interface Module (SPI)
Technical Data
I/O Registers
307

Related parts for MC68HC908AB32