MC68HC908AB32 MOTOROLA [Motorola, Inc], MC68HC908AB32 Datasheet - Page 211

• Manufacturer Part Number: MC68HC908AB32
• Description: HCMOS Microcontroller Unit
• Manufacturer: MOTOROLA [Motorola, Inc]

MC68HC908AB32
MOTOROLA
NOTE:
NOTE:
—
Rev. 1.0
TOF — TIMB Overflow Flag Bit
TOIE — TIMB Overflow Interrupt Enable Bit
TSTOP — TIMB Stop Bit
Do not set the TSTOP bit before entering wait mode if the TIMB is
required to exit wait mode.
TRST — TIMB Reset Bit
Setting the TSTOP and TRST bits simultaneously stops the TIMB
counter at a value of $0000.
This read/write flag is set when the TIMB counter resets to $0000 after
reaching the modulo value programmed in the TIMB counter modulo
registers. Clear TOF by reading the TIMB status and control register
when TOF is set and then writing a logic zero to TOF. If another TIMB
overflow occurs before the clearing sequence is complete, then
writing logic zero to TOF has no effect. Therefore, a TOF interrupt
request cannot be lost due to inadvertent clearing of TOF. Reset
clears the TOF bit. Writing a logic one to TOF has no effect.
This read/write bit enables TIMB overflow interrupts when the TOF bit
becomes set. Reset clears the TOIE bit.
This read/write bit stops the TIMB counter. Counting resumes when
TSTOP is cleared. Reset sets the TSTOP bit, stopping the TIMB
counter until software clears the TSTOP bit.
Setting this write-only bit resets the TIMB counter and the TIMB
prescaler. Setting TRST has no effect on any other registers.
Counting resumes from $0000. TRST is cleared automatically after
the TIMB counter is reset and always reads as logic zero. Reset
clears the TRST bit.
Freescale Semiconductor, Inc.
For More Information On This Product,
1 = TIMB counter has reached modulo value
0 = TIMB counter has not reached modulo value
1 = TIMB overflow interrupts enabled
0 = TIMB overflow interrupts disabled
1 = TIMB counter stopped
0 = TIMB counter active
1 = Prescaler and TIMB counter cleared
0 = No effect
Timer Interface Module B (TIMB)
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Timer Interface Module B (TIMB)
Technical Data
I/O Registers
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