UJA1061TW PHILIPS [NXP Semiconductors], UJA1061TW Datasheet - Page 53

• Manufacturer Part Number: UJA1061TW
• Description: Low speed CAN/LIN system basis chip
• Manufacturer: PHILIPS [NXP Semiconductors]

Philips Semiconductors
6.15
Many register contents are unaffected by an external reset event (edge at pin RSTN), for example, the CAN physical
layer register will not reset the bus failure information. Since an externally-forced reset event sets the UJA1061 into
start-up, the same behaviour will occur as in Start-up mode with the exception of the V3 configuration flag V3C and the
INH control flags (IC1 and IC2) in the system configuration register.
Table 18 Mode register: status at reset
Table 19 System status register: status at reset
Note
1. Depends on history.
2004 Mar 22
NWP
OM
SDM
EN
CM
RSS
LWS
EWS
TWS
SDMS
ENS
PWONS
SYMBOL
SYMBOL
Low speed CAN/LIN system basis chip
Register configurations at reset
Nominal Watchdog
Period
Operating Mode
Software Development
Mode
ENable
CAN Mode
Reset Source Status
Level Wake Status
Edge Wake Status
Temperature Warning
Status
Software Development
Mode Status
Enable Status
Power-on Status
NAME
NAME
256 ms start-up
0 (EN = LOW)
0 (EN = LOW)
POWER-ON
POWER-ON
wait on init
0 (auto)
0000
0
0
0
0
0
1
53
0001 or 0010 or 0011 or
0100 or 0111 or 1000 or
1001 or 1010 or 1011 or
1101 or 1110 or 1111
EXTERNAL RESET
EXTERNAL RESET
256 ms start-up
0 (EN = LOW)
0 (EN = LOW)
actual status
START-UP/
START-UP/
wait on init
no change
no change
no change
0 (auto)
0
0
(1)
0000 or 0110 or 1100 or
1110
Objective specification
256 ms start-up
0 (EN = LOW)
0 (EN = LOW)
actual status
RESTART
wait on init
no change
no change
no change
RESTART
0 (auto)
UJA1061
0
0
(1)