UJA1061TW PHILIPS [NXP Semiconductors], UJA1061TW Datasheet - Page 46

• Manufacturer Part Number: UJA1061TW
• Description: Low speed CAN/LIN system basis chip
• Manufacturer: PHILIPS [NXP Semiconductors]

Philips Semiconductors
6.14.10 P
This register has write access only in Normal and Standby modes; it allows the CAN and the LIN physical layer to be
configured.
Table 11 PLC - Physical Layer Control register (address 11) bit description
2004 Mar 22
Low speed CAN/LIN system basis chip
15, 14
BIT
13
12
11
10
9
8
7
6
5
4
3
2
HYSICAL
SYMBOL
A1, A0
CPNC
COTC
L42C
RRS
CRC
CTC
LSC
RO
L
AYER
register address
Read Register Select
Read Only
reserved
CAN Partial
Networking Control
CAN Off-line Time
Control
CAN Transmitter
Control
CAN Receiver
Control
reserved
reserved
LIN Slope Control
reserved
LIN 42 V Control
C
ONTROL REGISTER
DESCRIPTION
VALUE
1
1
11
1
0
1
0
0
1
0
1
0
0
0
0
0
1
0
0
1
0
(1)
(2)
46
select Physical Layer Control register
read the General Purpose Feedback register 1 (GPF1)
read the Physical Layer Control Feedback register (PLCF)
read the register selected by RRS without writing to the
Physical Layer Control register
read the register selected by RRS and write to Physical
Layer Control register
reserved for future use; should always be set to logic 0 in
order to secure compatibility with future functions which will
be activated by a logic 1
allows Selective Sleep state to be entered; cleared
whenever the UJA1061 enters On-line or Active mode
no Selective Sleep mode allowed (default)
256 ms time until CAN falls into Off-line (400 ms after
Wake-up)
64 ms time until CAN falls into Off-line (400 ms after
Wake-up)
CAN transmitter is disabled; allows setting ‘listen only’
behaviour; set also due to a detected short at V2 or a
RXDC recessive or TXDC dominant clamping failure
CAN transmitter is enabled
TXD signal is forwarded to RXD during CAN
transmitter OFF
TXD signal is not forwarded to RXD during CAN
transmitter OFF
reserved for future use; should always be set to logic 0 in
order to secure compatibility with future functions which will
be activated by a logic 1
reserved for future use; should always be set to logic 0 in
order to secure compatibility with future functions which will
be activated by a logic 1
up to 10 kbit/s
up to 20 kbit/s
reserved for future use; should always be set to logic 0 in
order to secure compatibility with future functions which will
be activated by a logic 1
LIN termination supplied out of BAT42
LIN termination is always related to BAT14
FUNCTION
Objective specification
UJA1061