UJA1061TW PHILIPS [NXP Semiconductors], UJA1061TW Datasheet - Page 30

• Manufacturer Part Number: UJA1061TW
• Description: Low speed CAN/LIN system basis chip
• Manufacturer: PHILIPS [NXP Semiconductors]

Philips Semiconductors
The following SPI interface signals are implemented:
The SPI interface can be accessed only when pin RSTN
(input channel of RSTN) is set HIGH.
Possible SPI failures are:
2004 Mar 22
handbook, full pagewidth
SCS - SPI chip select; active LOW
SCK - SPI clock; default level is LOW due to low-power
concept
SDI - SPI data input
SDO - SPI data output; floating when pin SCS is HIGH.
SPI clock count failure (wrong number of clock cycles
during one SPI access). Within one SCS cycle only
16 clock periods are allowed. Any deviation from the
16 clock cycles results in an SPI failure interrupt, if
enabled. The access is ignored by the UJA1061. In
Start-up and Restart mode, a reset is forced instead of
an interrupt
Low speed CAN/LIN system basis chip
SDO
SCS
SCK
SDI
floating
X
X
sampled
01
MSB
MSB
02
14
14
Fig.13 SPI timing protocol.
03
13
13
30
With a read-only access to the system status register or
the system diagnosis register which, with the mode
register, share the same SPI address, the data written to
the mode register is ‘don’t care’ and is ignored. Reading
these two system registers is allowed at any time
independent of watchdog window cycles.
04
Wrong mode register code. The following events result
in an immediate system reset without interrupt
according to the state diagram of the system controller
– Mode other than initializing Normal mode selected
– Initializing Flash mode outside of Start-up mode or
– Bit WDD set in the mode register; this bit may only be
– Illegal watchdog period coding, see Section 6.14.2.
Illegal mode register code during Normal or Standby
mode of the UJA1061.
12
12
within mode register in Start-up or Restart mode
within Start-up mode without previous Flash
sequence
set via the special mode register
15
01
01
16
LSB
LSB
Objective specification
UJA1061
floating
MCE634
X