LPC47M172_07 SMSC [SMSC Corporation], LPC47M172_07 Datasheet - Page 97

• Manufacturer Part Number: LPC47M172_07
• Description: Advanced I/O Controller with Motherboard GLUE Logic
• Manufacturer: SMSC [SMSC Corporation]

Note 1:
Note 2:
7.10.1 Extended Capabilities Parallel Port
7.10.2 Vocabulary
SMSC LPC47M172
nWAIT
nDATASTB
nRESET
nADDRSTB
PE
SLCT
nERR
SIGNAL
SPP and EPP can use 1 common register.
nWrite is the only EPP output that can be over-ridden by SPP control port during an EPP cycle. For
correct EPP read cycles, PCD is required to be a low.
ECP provides a number of advantages, some of which are listed below. The individual features are
explained in greater detail in the remainder of this section.
High performance half-duplex forward and reverse channel Interlocked handshake, for fast reliable transfer
Optional single byte RLE compression for improved throughput (64:1) Channel addressing for low-cost
peripherals Maintains link and data layer separation Permits the use of active output drivers permits the
use of adaptive signal timing Peer-to-peer capability.
The following terms are used in this document:
assert:
forward:
reverse:
Pword:
1
0
These terms may be considered synonymous:
EPP
PeriphClk, nAck
HostAck, nAutoFd
PeriphAck, Busy
nPeriphRequest, nFault
When a signal asserts it transitions to a "true" state, when a signal deasserts it transitions to a
"false" state.
Host to Peripheral communication.
Peripheral to Host communication
A port word; equal in size to the width of the LPC interface. For this implementation, PWord is
always 8 bits.
A high level.
A low level.
nWait
nData Strobe
nReset
Address
Strobe
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Status
Error
EPP NAME
TYPE
O
O
O
I
I
I
I
DATASHEET
This signal is active low. It is driven inactive as a positive
acknowledgement from the device that the transfer of data is
completed. It is driven active as an indication that the device
is ready for the next transfer.
This signal is active low. It is used to denote data read or
write operation.
This signal is active low. When driven active, the EPP
device is reset to its initial operational mode.
This signal is active low. It is used to denote address read or
write operation.
Same as SPP mode.
Same as SPP mode.
Same as SPP mode.
Page 97
EPP DESCRIPTION
Advanced I/O Controller with Motherboard GLUE Logic
SMSC/Non-SMSC Register Sets (Rev. 01-11-07)
Datasheet