LPC47M172_07 SMSC [SMSC Corporation], LPC47M172_07 Datasheet - Page 112

• Manufacturer Part Number: LPC47M172_07
• Description: Advanced I/O Controller with Motherboard GLUE Logic
• Manufacturer: SMSC [SMSC Corporation]

Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
7.23.3 SER_IRQ Data Frame
7.23.4 Stop Cycle Control
SMSC/Non-SMSC Register Sets (Rev. 01-11-07)
Once a Start Frame has been initiated, the LPC47M172 will watch for the rising edge of the Start Pulse
and start counting IRQ/Data Frames from there. Each IRQ/Data Frame is three clocks: Sample phase,
Recovery phase, and Turn-around phase. During the Sample phase the LPC47M172 drives the SER_IRQ
low, if and only if, its last detected IRQ/Data value was low. If its detected IRQ/Data value is high,
SER_IRQ is left tri-stated. During the Recovery phase the LPC47M172 drives the SER_IRQ high, if and
only if, it had driven the SER_IRQ low during the previous Sample Phase. During the Turn-around Phase
the LPC47M172 tri-states the SER_IRQ. The LPC47M172 drives the SER_IRQ line low at the appropriate
sample point if its associated IRQ/Data line is low, regardless of which device initiated the Start Frame.
The Sample Phase for each IRQ/Data follows the low to high transition of the Start Frame pulse by a
number of clocks equal to the IRQ/Data Frame times three, minus one. (e.g. The IRQ5 Sample clock is
the sixth IRQ/Data Frame, (6 x 3) - 1 = 17
SER_IRQ Period 14 is used to transfer IRQ13. Logical devices FDC, Parallel Port, Serial Port, and
Keyboard have IRQ13 as a choice for their primary interrupt.
Once all IRQ/Data Frames have completed the Host Controller will terminate SER_IRQ activity by initiating
a Stop Frame. Only the Host Controller can initiate the Stop Frame. A Stop Frame is indicated when the
SER_IRQ is low for two or three clocks. If the Stop Frame’s low time is two clocks then the next SER_IRQ
Cycle’s sampled mode is the Quiet mode; and any SER_IRQ device may initiate a Start Frame in the
second clock or more after the rising edge of the Stop Frame’s pulse. If the Stop Frame’s low time is three
clocks then the next SER_IRQ Cycle’s sampled mode is the Continuous mode; and only the Host
Controller may initiate a Start Frame in the second clock or more after the rising edge of the Stop Frame’s
pulse.
SER_IRQ PERIOD
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
SER_IRQ Sampling Periods
DATASHEET
SIGNAL SAMPLED
Not Used
th
IRQ10
IRQ11
IRQ12
IRQ13
IRQ14
IRQ15
IRQ1
IRQ2
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
IRQ8
IRQ9
clock after the rising edge of the Start Pulse).
Page 112
# OF CLOCKS PAST START
11
14
17
20
23
26
29
32
35
38
41
44
47
2
5
8
SMSC LPC47M172