LPC47M172_07 SMSC [SMSC Corporation], LPC47M172_07 Datasheet - Page 48

• Manufacturer Part Number: LPC47M172_07
• Description: Advanced I/O Controller with Motherboard GLUE Logic
• Manufacturer: SMSC [SMSC Corporation]

Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
BITS 0 – 1 DATA RATE SELECT
BIT 2 NOPREC
BIT 3 DMAEN
BITS 4 – 6 UNDEFINED
BIT 7 DSKCHG
6.4.11 Configuration Control Register (CCR)
PC/AT and PS/2 Modes
BIT 0 and 1 DATA RATE SELECT 0 and 1
BIT 2 – 7 RESERVED
PS/2 Model 30 Mode
BIT 0 and 1 DATA RATE SELECT 0 and 1
BIT 2 NO PRECOMPENSATION
SMSC/Non-SMSC Register Sets (Rev. 01-11-07)
These bits control the data rate of the floppy controller. See Table 6.8 for the settings corresponding to the
individual data rates. The data rate select bits are unaffected by a software reset, and are set to 250 Kbps
after a hardware reset.
This bit reflects the value of NOPREC bit set in the CCR register.
This bit reflects the value of DMAEN bit set in the DOR register bit 3.
Always read as a logic “0”
This bit monitors the pin of the same name and reflects the opposite value seen on the disk cable or the
value programmed in the Force Disk Change Register (see Power Control/Runtime Register Block runtime
register at offset 0x18).
Address 3F7 WRITE ONLY
These bits determine the data rate of the floppy controller. See Table 6.8 for the appropriate values.
Should be set to a logical “0”
These bits determine the data rate of the floppy controller. See Table 6.8 for the appropriate values.
This bit can be set by software, but it has no functionality. It can be read by bit 2 of the DSR when in
Model 30 register mode. Unaffected by software reset.
RESET
RESET
COND.
COND.
N/A
N/A
7
0
7
0
N/A
N/A
6
0
6
0
DATASHEET
N/A
N/A
5
0
5
0
Page 48
N/A
N/A
4
0
4
0
N/A
N/A
3
0
3
0
NOPREC DRATE
N/A
N/A
2
0
2
DRATE
SEL1
SEL1
1
1
1
1
DRATE
DRATE
SEL0
SEL0
SMSC LPC47M172
0
0
0
0