LPC47M172_07 SMSC [SMSC Corporation], LPC47M172_07 Datasheet - Page 113

• Manufacturer Part Number: LPC47M172_07
• Description: Advanced I/O Controller with Motherboard GLUE Logic
• Manufacturer: SMSC [SMSC Corporation]

7.23.5 Latency
7.23.6 EOI/ISR Read Latency
7.23.7 AC/DC Specification Issue
7.23.8 Reset and Initialization
7.24
SMSC LPC47M172
Latency for IRQ/Data updates over the SER_IRQ bus in bridge-less systems with the minimum Host
supported IRQ/Data Frames of seventeen, will range up to 96 clocks (3.84μS with a 25MHz PCI Bus or
2.88uS with a 33MHz PCI Bus). If one or more PCI to PCI Bridge is added to a system, the latency for
IRQ/Data updates from the secondary or tertiary buses will be a few clocks longer for synchronous buses,
and approximately double for asynchronous buses.
Any serialized IRQ scheme has a potential implementation issue related to IRQ latency. IRQ latency could
cause an EOI or ISR Read to precede an IRQ transition that it should have followed. This could cause a
system fault.
mitigated. The recommended solution is to delay EOIs and ISR Reads to the interrupt controller by the
same amount as the SER_IRQ Cycle latency in order to ensure that these events do not occur out of
order.
All SER_IRQ agents must drive / sample SER_IRQ synchronously related to the rising edge of PCI bus
clock. The SER_IRQ pin uses the electrical specification of PCI bus. Electrical parameters will follow PCI
spec. section 4, sustained tri-state.
The SER_IRQ bus uses nPCI_RESET as its reset signal. The SER_IRQ pin is tri-stated by all agents
while nPCI_RESET is active. With reset, SER_IRQ Slaves are put into the (continuous) IDLE mode. The
Host Controller is responsible for starting the initial SER_IRQ Cycle to collect system’s IRQ/Data default
values. The system then follows with the Continuous/Quiet mode protocol (Stop Frame pulse width) for
subsequent SER_IRQ Cycles. It is Host Controller’s responsibility to provide the default values to 8259’s
and other system logic before the first SER_IRQ Cycle is performed. For SER_IRQ system suspend,
insertion, or removal application, the Host controller should be programmed into Continuous (IDLE) mode
first. This is to guarantee SER_IRQ bus is in IDLE state before the system configuration changes.
Interrupt Generating Registers
The LPC47M172 contains on-chip Interrupt Generating Registers to enable external software to generate
IRQ1 through IRQ15 on the Serial IRQ Interface. These registers, INT_GEN1 and INT_GEN2, are located
in the Power Control Block/Runtime Register Block, at offsets 0x1B and 0x1C, respectively, from the base
address setting (set at Index 0x60 and 0x61 Configuration Registers). See Chapter 8 Power Control
Runtime Registers and Chapter 10 Runtime Register Block Runtime Registers.
Registers INT_GEN1 and INT_GEN2 are enabled to output to the Serial IRQ stream by setting Power
Control Block Configuration Register, at Index 0xF1, Bit [0] to ‘1’. When Bit [0] is set to ‘0’, INT_GEN1 and
INT_GEN2 are prevented from outputting to the Serial IRQ stream.
Writing Bits 0 through 7 to ‘0’ in registers INT_GEN1 and INT_GEN2 enable the corresponding interrupt
(INT1 through INT15) to be asserted (made active) in the Serial IRQ stream. Producing an interrupt in the
Serial IRQ stream by writing these bits to ‘0’ overrides other interrupt sources for the Serial IRQ stream.
No other functional logic in the LPC47M172 sets bits in these registers. The asserted interrupt in the Serial
IRQ stream from registers INT_GEN1 and INT_GEN2 is removed by writing the corresponding bit to ‘1’.
The host interrupt controller is responsible for ensuring that these latency issues are
DATASHEET
Page 113
Advanced I/O Controller with Motherboard GLUE Logic
SMSC/Non-SMSC Register Sets (Rev. 01-11-07)
Datasheet