LPC47M172_07 SMSC [SMSC Corporation], LPC47M172_07 Datasheet - Page 135

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LPC47M172_07

Manufacturer Part Number
LPC47M172_07
Description
Advanced I/O Controller with Motherboard GLUE Logic
Manufacturer
SMSC [SMSC Corporation]
Datasheet
Note:
7.31.4 Reference Timings
7.32
7.33
SMSC LPC47M172
The maximum voltage drop across the diode is 350mV.
See Figure 13.25 to Figure 13.28 in the “Timing Diagrams” section.
IDE Reset Output Pin
nIDE_RST is an open drain buffered copy of nPCI_RESET. This signal requires an external 1kohm pull-up
to VCC5V.
This signal will be low when VCC5V=0 since it is externally pulled up to VCC5V.
See Table 13.1 for nIDE_RSTDRV timing.
PCI Reset Output Pins
The nPCIRST_OUT is 3.3V buffered copy of nPCI_RESET. The nPCIRST_OUT2 is 3.3V buffered copy of
nPCI_RESET.
The nPCIRST_OUT and nPCIRST_OUT2 signals will be low when VCC=0.
nIDE_RSTDRV
NAME
nPCI_RESET (Input)
Table 7.28 - nIDE_RSTDRV Truth Table
OD8
BUFFER
0
1
Table 7.27 - nIDE_RSTDRV Pin
DATASHEET
Figure 7.9 - REF5V_STBY
VCC
POWER
Page 135
WELL
SMSC I/O
Protection
Backdrive
nIDE_RSTDRV (Output)
IDE Reset Output
DESCRIPTION
Advanced I/O Controller with Motherboard GLUE Logic
Hi-Z
0
SMSC/Non-SMSC Register Sets (Rev. 01-11-07)
V_5P0_STBY
1k
Datasheet

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