LPC47M172_07 SMSC [SMSC Corporation], LPC47M172_07 Datasheet - Page 39

• Manufacturer Part Number: LPC47M172_07
• Description: Advanced I/O Controller with Motherboard GLUE Logic
• Manufacturer: SMSC [SMSC Corporation]

BIT 1 WRITE PROTECT
BIT 2 INDEX
BIT 3 HEAD SELECT
BIT 4 TRACK 0
BIT 5 STEP
BIT 6 DMA REQUEST
BIT 7 INTERRUPT PENDING
6.4.4
PS/2 Mode
BIT 0 MOTOR ENABLE 0
BIT 1 MOTOR ENABLE 1
BIT 2 WRITE GATE
SMSC/Non-SMSC Register Sets (Rev. 01-11-07)
Active high status of the WRITE PROTECT disk interface input. A logic “1” indicates that the disk is write
protected.
Active high status of the INDEX disk interface input.
Active low status of the HDSEL disk interface input. A logic “0” selects side 1 and a logic “1” selects side
0.
Active high status of the TRK0 disk interface input.
Active high status of the latched STEP disk interface output pin. This bit is latched with the STEP output
going active, and is cleared with a read from the DIR register, or with a hardware or software reset.
Active high status of the DMA request pending.
Active high bit indicating the state of the Floppy Disk Interrupt.
Status Register B (SRB)
Address 3F1 READ ONLY
This register is read-only and monitors the state of several disk interface pins in PS/2 and Model 30
modes. The SRB can be accessed at any time when in PS/2 mode. In the PC/AT mode the data bus pins
D0 – D7 are held in a high impedance state for a read of address 3F1.
Active high status of the MTR0 disk interface output pin. This bit is low after a hardware reset and
unaffected by a software reset.
Active high status of the MTR1 disk interface output pin. This bit is low after a hardware reset and
unaffected by a software reset.
Active high status of the WGATE disk interface output.
RESET
COND.
7
1
1
6
1
1
DATASHEET
DRIVE
SEL0
5
0
Page 39
TOGGLE
WDATA
4
0
TOGGLE
RDATA
3
0
Advanced I/O Controller with Motherboard GLUE Logic
WGATE
2
0
MOT
EN1
1
0
MOT
EN0
SMSC LPC47M172
0
0
Datasheet