TMC2250AG1C2 FAIRCHILD [Fairchild Semiconductor], TMC2250AG1C2 Datasheet - Page 6
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TMC2250AG1C2
Manufacturer Part Number
TMC2250AG1C2
Description
Matrix Multiplier 12 x 10 bit, 50 MHz
Manufacturer
FAIRCHILD [Fairchild Semiconductor]
Datasheet
1.TMC2250AG1C2.pdf
(23 pages)
PRODUCT SPECIFICATION
Pin Descriptions
6
Pin Name
Power
V
GND
Clock
CLK
Controls
MODE
CWE
Input/Output
A
B
C
DD
11-0
11-0
11-0
1,0
1,0
F3, H3, L7, C8,
E3, G3, J3, L4,
E11, D13, E12,
B10, A11, B11,
C10, A12, B12,
A5, C6, B6, A6,
A7, B7, A8, B8,
E13, F11, F12,
CPGA/PPGA/
L6, H11, C7,
A9, B9, A10,
G11, G12,
F13, G13,
C11, A13,
C12, B13,
H13, H12
C13, D12
J12, J13
MPGA
B4, A4
D11
C4
C5
C9
Pin Number
84, 83, 82, 81,
80, 79, 78, 77,
97, 96, 95, 94,
93, 92, 91, 90,
76, 75, 74, 73
89, 87, 86, 85
8, 16, 24, 34,
101, 100, 99,
42, 72, 106,
12, 20, 46,
111, 110,
109, 108,
107, 105,
104, 103,
102, 118
112, 113
MQFP
70, 71
114
88
98
Function
Supply
Voltage
Ground
System Clock
Mode Control
Coefficient
Write Enable
Data Input A
Data Input B
Data Input C
Pin Description
The TMC2250A operates from a single +5V supply.
All pins must be connected.
The TMC2250A operates from a single +5V supply.
All pins must be connected.
The TMC2250A operates from a single system clock
input. All timing specifications are referenced to the
rising edge of clock.
The TMC2250A will switch to the configuration
selected by the user (as shown in Table 3) on the
next clock. This registered control is usually static;
however, should the user wish to switch between
modes, the internal pipeline latencies of the device
must be taken into account. Valid data will not be
available at the outputs in the new configuration until
enough clocks in the new mode have passed to flush
the internal registers.
Data presented to the coefficient input ports (KA, KB,
and KC) will update three of the internal coefficient
storage registers, as indicated by the simultaneous
Coefficient Write Enable select, on the next clock.
See Table 4 and the Functional Block Diagram.
Data presented to the 12-bit registered data input
ports A, B, and C are latched into the multiplier input
registers for the currently selected configuration
(Table 3). In all modes except Mode 00, new data are
internally right-shifted to the next filter tap on each
rising edge of CLK.
REV. 1.0.2 10/25/00
TMC2250A