TMC2250AG1C2 FAIRCHILD [Fairchild Semiconductor], TMC2250AG1C2 Datasheet - Page 14
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TMC2250AG1C2
Manufacturer Part Number
TMC2250AG1C2
Description
Matrix Multiplier 12 x 10 bit, 50 MHz
Manufacturer
FAIRCHILD [Fairchild Semiconductor]
Datasheet
1.TMC2250AG1C2.pdf
(23 pages)
PRODUCT SPECIFICATION
4 x 2-Pixel Cascadeable Convolver
(Mode 11)
Similar to Mode 10, the 4 x 2 -Pixel convolver allows the use
to perform full-speed cubic convolution with only two
TMC2250A devices and the TMC2111A Pipeline Delay
Register to synchronize the cascade ports (see the Applica-
tions Discussion section).
Pixel data are side-loaded into ports A and B, multiplied by
the onboard coefficients, summed with the cascade input,
and half-LSB rounded to 16 bits. The four-cycle impulse
response emerges at the cascade output port 5 to 8 clock
cycles later. A new output word is available on every clock
cycle. Note that Multiplier KC2 is not used in this mode and
that its stored coefficient is ignored.
14
CLK
CWE
KA, KB, KC
DATA IN A, B
MODE
CASIN
CASOUT
K_1
01
1
K_2
10
Figure 7. 4 x 2-Pixel Convolver Impulse Response (Mode 11)
2
K_3
1.0
11
3
00
4
5
As shown below, the column of input pixel data is automati-
cally shifted one location to the right through the two rows of
multiplier input registers on every clock in anticipation of
two new input data words, effectively sliding the convolu-
tional window over one column in an image plane.
CASOUT(8)=
A(4)KA3(4)+A(3)KA2(3)+A(2)KA1(2)
+A(1)KB3(4)+B(4)KB3(4)+B(3)KB2(3)
+B(2)KB1(2)+B(1)KC1(2)+CASIN(5)
6
Q 8
11
7
KA 3 + KB 3
8
KA 2 + KB 2
9
KA 1 + KB 1
10
KC 1 + KC 3
REV. 1.0.2 10/25/00
11
Q 8
TMC2250A