TMC2250AG1C2 FAIRCHILD [Fairchild Semiconductor], TMC2250AG1C2 Datasheet - Page 10
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TMC2250AG1C2
Manufacturer Part Number
TMC2250AG1C2
Description
Matrix Multiplier 12 x 10 bit, 50 MHz
Manufacturer
FAIRCHILD [Fairchild Semiconductor]
Datasheet
1.TMC2250AG1C2.pdf
(23 pages)
PRODUCT SPECIFICATION
9-Tap FIR Filter Mode (01)
The architecture for this configuration is shown in Figure 4.
The user loads the desired coefficient set, presents input data
to ports A and B simultaneously (most applications will wire
the A and B inputs together), and receives the resulting 9-
sample response, half-LSB rounded to 16 bits, 5 to 13 clock
cycles later. A new output data word is available every clock
cycle.
The figure shows that the input data are automatically right-
shifted by one position through the row of multiplier input
registers on every clock in anticipation of a new input data
word.
10
CLK
CWE
KA, KB, KC
DATA IN A, B
MODE CONTROL
CASIN
CASOUT
K_1
01
1
K_2
10
2
K_3
1.0
11
3
Figure 3. 9-Tap FIR Filter Impulse Response (Mode 01)
4
5
6
7
KA 3
01
8
CASOUT(13) =
A(9)KA3(9)+A(8)KA2(8)+A(7)KA1(7)
Latency: Impulse in to center of 9-tap response =9 registers.
Cascade In to Cascade Out=4 registers.
KA 2
+B(6)KB3(9)+B(5)KB2(8)+B(4)KB1(7)
+B(3)KC3(9)+B(2)KC2(8)+B(1)KC1(7)
9
KA 1
10
KB 3
+CASIN(10)
11
KB 2
12
Q 13
KB 1
13
KC 3
14
KC 2
REV. 1.0.2 10/25/00
15
KC 1
16
TMC2250A
Q 13
17