TMC2250AG1C2 FAIRCHILD [Fairchild Semiconductor], TMC2250AG1C2 Datasheet - Page 2
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TMC2250AG1C2
Manufacturer Part Number
TMC2250AG1C2
Description
Matrix Multiplier 12 x 10 bit, 50 MHz
Manufacturer
FAIRCHILD [Fairchild Semiconductor]
Datasheet
1.TMC2250AG1C2.pdf
(23 pages)
PRODUCT SPECIFICATION
Functional Description
The TMC2250A is a nine-multiplier array with the internal bus
structure and summing adders needed to implement a 3 x 3
matrix multiplier (triple dot product) a cascadeable 9-tap FIR
filter, a 3 x 3-pixel convolver, or a 4 x 2-pixel convolver all in
one monolithic circuit. With a 50MHz guaranteed maximum
clock rate, this device offers video and imaging system
designers a single-chip solution to numerous common image
and signal-processing problems.
The three data input ports (A, B, C) accept 12-bit two's com-
plement integer data, which is also the format for the output
ports (X, Y, Z) in the matrix multiply mode (Mode 00). In the
filter configurations (Modes 01, 10, and 11) the cascade ports
assume 12-bit integer, 4-bit fractional two's complement data
on both input and output. The coefficient input ports (KA,
KB, KC) are always 10-bit two's complement fractional.
Table 1 details the bit weighting of the input and output data
in all configurations.
Operating Modes
The TMC2250A can implement four different digital filter
architectures. Upon selection of the desired function by the
user (MODE
paths and input and output buses appropriately. The output
ports (XC, YC and ZC) are configured in all filter modes a
16-bit Cascade In and Cascade Out ports so that multiple
devices can be connected to build larger filters. These modes
are described individually below. The I/O function configu-
rations for all four modes are shown in Table 1.
Definitions
The calculations performed by the TMC2250A in each mode
are also shown below, utilizing the following notation:
A(1), B(5), C(2), CASIN(3)
Indicates the data word presented to that input port during
the specified clock rising edge(x). Applies to all input ports
A
2
Table 1. Data Port Formatting by Mode
Mode
11-0
00
01
10
11
, B
11-0
A
A
A
A
A
11-0
11-0
11-0
11-0
11-0
, C
1-0
11-0
), the device reconfigures its internal data
B
B
B
B
B
, and CASIN
11-0
11-0
11-0
11-0
11-0
C
C
C
NC
NC
11-0
11-0
11-0
Inputs
15-0
KA
KA
KA
KA
KA
.
9-0
9-0
9-0
9-0
9-0
KB
KB
KB
KB
KB
9-0
9-0
9-0
9-0
9-0
KC9-0
KC9-0
KC9-0 CASIN
KC9-0 CASIN
KC9-0 CASIN
XC
X
Inputs/Output
KA1(1), KB3(4)
Indicates coefficient data stored in the specified one of the
nine onboard coefficient registers KA1 through KC3, as
shown in the block diagram for that mode, input during or
before the specified clock rising edge (x).
X(1), Y(4), Z(6), CASOUT (6)
Indicated data available at that output port t
specified clock rising edge (x). Applies to all output ports
X
Numeric Format
Table 2 shows the binary weightings of the input and output
ports of the TMC2250A. Although the internal sums of prod-
ucts could grow to 23 bits, in the matrix multiply mode
(Mode 00) the outputs X, Y and Z are rounded to yield 12-bit
integer words. Thus the output format is identical to the input
data format. In the filter configurations (Modes 01, 10, and
11) the cascade output is always half-LSB rounded to 16
bits, specifically 12 integer bits and 4 fractional guard bits,
with no overflow "headroom". The user is of course free to
half-LSB round the output word to any size less than 16 bits
by forcing a 1 into the bit position of the cascade input
immediately below the desired LSB. In all modes, bit
weighting is easily adjusted if desired by applying the same
scaling correction factor to both input and output data words.
If the coefficients are rescaled, the relative weightings of the
CASIN and CASOUT ports will differ accordingly.
Data Overflow
As shown in Table 2, the TMC2250A's matched input and
output data formats accommodate 0dB (unity) gain. There-
fore, the user must be aware of input conditions that could
lead to numeric overflow. Maximum input data and coeffi-
cient word sizes must be taken into account with the specific
algorithm performed to ensure that no overflow occurs.
11-0
11-0
11-0
15-4
15-4
15-4
, Y
11-0
CASIN
CASIN
CASIN
YC
Y
, Z
11-8
11-8
11-0
3-0
3-0
3-0
, and CASOUT
Y
Y
NC
NC
NC
7-4
7-4
CASOUT
CASOUT
CASOUT
YC3-0
15-0
Y
3-0
Outputs
.
3-0
3-0
3-0
REV. 1.0.2 10/25/00
DO
CASOUT
CASOUT
CASOUT
after that
ZC
Z
TMC2250A
11-0
11-0
15-4
15-4
15-4