MC68HC705C4ACB MOTOROLA [Motorola, Inc], MC68HC705C4ACB Datasheet - Page 59

• Manufacturer Part Number: MC68HC705C4ACB
• Description: Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

4.3.6 SPI Interrupts
MC68HC705C4A • MC68HSC705C4A — Rev. 3.0
MOTOROLA
The SPI can generate these interrupts:
Setting the I bit in the condition code register disables all SPI interrupts.
•
•
•
•
•
•
SCI Receiver Overrun Interrupt — The overrun bit (OR)
indicates that a received byte is lost because software has not
read the previously received byte. OR becomes set when a byte
shifts into the receive shift register before software reads the word
already in the SCI data register. OR generates an interrupt
request if the receive interrupt enable bit (RIE) is set also.
SCI Receiver Input Idle Interrupt — The receiver input idle bit
(IDLE) indicates that the SCI receiver input is not receiving data.
IDLE becomes set when 10 or 11 consecutive logic ones appear
on the receiver input. IDLE generates an interrupt request if the
idle line interrupt enable bit (ILIE) is set also.
SPI transmission complete interrupt
SPI mode fault interrupt
SPI Transmission Complete Interrupt — The SPI flag bit (SPIF)
in the SPI status register indicates the completion of an SPI
transmission. SPIF becomes set when a byte shifts into or out of
the SPI data register. SPIF generates an interrupt request if the
SPIE bit is set also.
SPI Mode Fault Interrupt — The mode fault bit (MODF) in the SPI
status register indicates an SPI mode error. MODF becomes set
when a logic 0 occurs on the PD5/SS pin while the master bit
(MSTR) in the SPI control register is set. MODF generates an
interrupt request if the SPIE bit is set also.
Interrupts
Interrupt Sources
Technical Data
Interrupts
59