MC68HC705C4ACB MOTOROLA [Motorola, Inc], MC68HC705C4ACB Datasheet - Page 140
MC68HC705C4ACB
Manufacturer Part Number
MC68HC705C4ACB
Description
Microcontrollers
Manufacturer
MOTOROLA [Motorola, Inc]
Datasheet
1.MC68HC705C4ACB.pdf
(210 pages)
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Serial Peripheral Interface (SPI)
11.6 Serial Clock Polarity and Phase
Technical Data
140
CPHA
0
1
0
1
CPOL
CAPTURE STROBE
0
0
1
1
SDO/SDI
SCK (A)
SCK (B)
SCK (C)
SCK (D)
SS
To accommodate the different serial communication requirements of
peripheral devices, software can change the phase and polarity of the
SPI serial clock. The clock polarity bit (CPOL) and the clock phase bit
(CPHA), both in the SPCR, control the timing relationship between the
serial clock and the transmitted data.
and CPHA bits affect the clock/data timing.
Figure 11-5. Two Master/Slaves and Three Slaves Block Diagram
MASTER/SLAVE
Figure 11-6. SPI Clock/Data Timing
MSB
PD2/MISO
PD3/MOSI
MCU 1
PORT
PD4/SCK
I/O
PD5/SS
Serial Peripheral Interface (SPI)
0
1
2
3
BIT 6
SLAVE MCU 2
BIT 5
BIT 4
MC68HC705C4A • MC68HSC705C4A — Rev. 3.0
SLAVE MCU 1
BIT 3
Figure 11-6
BIT 2
SLAVE MCU 0
shows how the CPOL
BIT 1
MASTER/SLAVE
PD2/MISO
PD3/MOSI
PD4/SCK
PD5/SS
0
1
2
3
LSB
MCU 2
PORT
MOTOROLA
I/O
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