MC68HC705C4ACB MOTOROLA [Motorola, Inc], MC68HC705C4ACB Datasheet - Page 54

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MC68HC705C4ACB

Manufacturer Part Number
MC68HC705C4ACB
Description
Microcontrollers
Manufacturer
MOTOROLA [Motorola, Inc]
Datasheet
Interrupts
Technical Data
54
CONNECTION
USED WITH
NORMALLY
WIRED-OR
INTERRUPT
IRQ PIN
a. Edge-Sensitive Trigger Condition. The minimum pulse width (t
b. Level-Sensitive Trigger Condition. If the interrupt line remains low after servicing an interrupt, then the
or 250 ns (f
execute the interrupt service routine plus 19 t
CPU continues to recognize an interrupt.
(INTERNAL)
IRQ
PIN
IRQ
.
.
.
IRQ
1
n
Figure 4-1. External Interrupt Internal Function Diagram
OP
EDGE- AND LEVEL-SENSITIVE TRIGGER
V
= 1 MHz). The period t
DD
OPTION REGISTER
Figure 4-2. External Interrupt Timing
D
C
t
IRQ LATCH
ILIH
R
Q
Q
ILIL
t
should not be less than the number of t
ILIH
CYC
t
ILIL
Interrupts
cycles.
I BIT (CCR)
MC68HC705C4A • MC68HSC705C4A — Rev. 3.0
ILIH)
is either 125 ns (f
POR
INTERNAL RESET (COP)
EXTERNAL RESET
EXTERNAL INTERRUPT BEING SERVICED
(VECTOR FETCH)
CYC
EXTERNAL
INTERRUPT
REQUEST
cycles it takes to
OP
= 2.1 MHz)
MOTOROLA

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