PIC18F2221 MICROCHIP [Microchip Technology], PIC18F2221 Datasheet - Page 29

• Manufacturer Part Number: PIC18F2221
• Description: 28/40/44-Pin Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology
• Manufacturer: MICROCHIP [Microchip Technology]

2.6.4
The 4x Phase Locked Loop (PLL) can be used with the
internal oscillator block to produce faster device clock
speeds than are normally possible with the internal
oscillator sources. When enabled, the PLL produces a
clock speed of 16 MHz or 32 MHz.
Unlike HSPLL mode, the PLL is controlled through
software. The control bit, PLLEN (OSCTUNE<6>), is
used to enable or disable its operation.
The PLL is available when the device is configured to
use the internal oscillator block as its primary clock
source (FOSC3:FOSC0 = 1001 or 1000). Additionally,
the PLL will only function when the selected output fre-
quency is either 4 MHz or 8 MHz (OSCCON<6:4> = 111
or 110). If both of these conditions are not met, the PLL
is disabled and the PLLEN bit remains clear (writes are
ignored).
REGISTER 2-1:
© 2007 Microchip Technology Inc.
bit 7
bit 6
bit 5
bit 4-0
PLL IN INTOSC MODES
OSCTUNE: OSCILLATOR TUNING REGISTER
INTSRC: Internal Oscillator Low-Frequency Source Select bit
1 = 31.25 kHz device clock derived from 8 MHz INTOSC source (divide-by-256 enabled)
0 = 31 kHz device clock derived directly from INTRC internal oscillator
PLLEN: Frequency Multiplier PLL for INTOSC Enable bit
1 = PLL enabled for INTOSC (4 MHz and 8 MHz only)
0 = PLL disabled
Unimplemented: Read as ‘0’
TUN4:TUN0: Frequency Tuning bits
01111 = Maximum frequency
•
•
00001
00000 = Center frequency. Oscillator module is running at the calibrated frequency.
11111
•
•
10000 = Minimum frequency
bit 7
Legend:
R = Readable bit
-n = Value at POR
INTSRC
R/W-0
Note 1: Available only in certain oscillator configurations; otherwise, this bit is unavailable
and reads as ‘0’. See Section 2.6.4 “PLL in INTOSC Modes” for details.
PLLEN
R/W-0
•
•
•
•
(1)
U-0
Preliminary
—
W = Writable bit
‘1’ = Bit is set
R/W-0
TUN4
2.6.5
The factory calibrates the internal oscillator block
output (INTOSC) for 8 MHz. However, this frequency
may drift as V
affect the controller operation in a variety of ways. It is
possible to adjust the INTOSC frequency by modifying
the value in the OSCTUNE register. Depending on the
device, this may have no effect on the INTRC clock
source frequency.
Tuning the INTOSC source requires knowing when to
make the adjustment, in which direction it should be
made and in some cases, how large a change is
needed. Three compensation techniques are discussed
in
EUSART”, Section 2.6.5.2 “Compensating with the
Timers” and Section 2.6.5.3 “Compensating with the
CCP Module in Capture Mode” but other techniques
may be used.
PIC18F4321 FAMILY
Section 2.6.5.1
R/W-0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
TUN3
INTOSC FREQUENCY DRIFT
DD
(1)
or temperature changes and can
R/W-0
TUN2
“Compensating
x = Bit is unknown
R/W-0
TUN1
DS39689E-page 27
with
R/W-0
TUN0
bit 0
the