PIC18F2221 MICROCHIP [Microchip Technology], PIC18F2221 Datasheet - Page 126

• Manufacturer Part Number: PIC18F2221
• Description: 28/40/44-Pin Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology
• Manufacturer: MICROCHIP [Microchip Technology]

PIC18F4321 FAMILY
11.1
Timer0 can operate as either a timer or a counter; the
mode is selected with the T0CS bit (T0CON<5>). In
Timer mode (T0CS = 0), the module increments on
every clock by default unless a different prescaler value
is selected (see Section 11.3 “Prescaler”). If the
TMR0 register is written to, the increment is inhibited
for the following two instruction cycles. The user can
work around this by writing an adjusted value to the
TMR0 register.
The Counter mode is selected by setting the T0CS bit
(= 1). In this mode, Timer0 increments either on every
rising or falling edge of pin RA4/T0CKI. The increment-
ing edge is determined by the Timer0 Source Edge
Select bit, T0SE (T0CON<4>); clearing this bit selects
the rising edge. Restrictions on the external clock input
are discussed below.
An external clock source can be used to drive Timer0;
however, it must meet certain requirements to ensure
that the external clock can be synchronized with the
FIGURE 11-1:
FIGURE 11-2:
DS39689E-page 124
Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale.
T0CKI pin
Note:
T0CKI pin
Timer0 Operation
T0SE
T0CS
T0PS2:T0PS0
PSA
Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale.
F
OSC
T0SE
T0CS
T0PS2:T0PS0
PSA
/4
F
OSC
TIMER0 BLOCK DIAGRAM (8-BIT MODE)
TIMER0 BLOCK DIAGRAM (16-BIT MODE)
/4
0
1
0
1
Programmable
Prescaler
Programmable
3
Prescaler
3
1
0
Preliminary
1
0
(2 T
Sync with
Internal
OSC
Clocks
(2 T
Delay)
Sync with
Internal
OSC
Clocks
internal phase clock (T
synchronization and the onset of incrementing the
timer/counter.
11.2
TMR0H is not the actual high byte of Timer0 in 16-bit
mode; it is actually a buffered version of the real high
byte of Timer0 which is not directly readable nor
writable (refer to Figure 11-2). TMR0H is updated with
the contents of the high byte of Timer0 during a read of
TMR0L. This provides the ability to read all 16 bits of
Timer0 without having to verify that the read of the high
and low byte were valid, due to a rollover between
successive reads of the high and low byte.
Similarly, a write to the high byte of Timer0 must also
take place through the TMR0H Buffer register. The high
byte is updated with the contents of TMR0H when a
write occurs to TMR0L. This allows all 16 bits of Timer0
to be updated at once.
Delay)
Timer0 Reads and Writes in
16-Bit Mode
TMR0L
8
8
TMR0L
8
8
OSC
© 2007 Microchip Technology Inc.
High Byte
TMR0H
TMR0
8
). There is a delay between
8
Set
TMR0IF
on Overflow
Internal Data Bus
8
Internal Data Bus
Set
TMR0IF
on Overflow
Read TMR0L
Write TMR0L