PIC18F2221 MICROCHIP [Microchip Technology], PIC18F2221 Datasheet - Page 270

• Manufacturer Part Number: PIC18F2221
• Description: 28/40/44-Pin Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology
• Manufacturer: MICROCHIP [Microchip Technology]

PIC18F4321 FAMILY
23.5
The overall structure of the code protection on the
PIC18 Flash devices differs significantly from other
PIC
The user program memory is divided into three blocks.
One of these is a boot block of variable size. The
remainder of the memory is divided into two blocks on
binary boundaries.
FIGURE 23-5:
DS39689E-page 268
®
devices.
Boot Block
2K words
1K word
1K word
11/10
Block 0
Block 1
Program Verification and
Code Protection
Unimplemented
(PIC18FX321)
Reads all ‘0’s
1.5K words
Boot Block
512 words
2K words
8 Kbytes
CODE-PROTECTED PROGRAM MEMORY FOR PIC18F4321 FAMILY DEVICES
Block 0
Block 1
01
MEMORY SIZE/DEVICE
1.75K words
BBSIZ<1:0>
Boot Block
256 words
2K words
Block 0
Block 1
00
11/10/01
0.5K words
Preliminary
Boot Block
512 words
1K word
Block 0
Block 1
Unimplemented
(PIC18FX221)
Reads all ‘0’s
4 Kbytes
Each of the three blocks has three code protection bits
associated with them. They are:
• Code-Protect bit (CPn)
• Write-Protect bit (WRTn)
• External Block Table Read bit (EBTRn)
Figure 23-5 shows the program memory organization
for 4 and 8-Kbyte devices and the specific code
protection bit associated with each block. The actual
locations of the bits are summarized in Table 23-3.
0.75K words
Boot Block
256 words
1K word
Block 0
Block 1
00
000000h
0001FFh
000200h
0003FFh
000400h
0007FFh
000800h
000FFFh
001000h
001FFFh
002000h
1FFFFFh
Address
Range
© 2007 Microchip Technology Inc.
(Unimplemented Memory
Block Code Protection
CPB, WRTB, EBTRB
CP0, WRT0, EBTR0
CP1, WRT1, EBTR1
Controlled By:
Space)