PIC18F2221 MICROCHIP [Microchip Technology], PIC18F2221 Datasheet - Page 27

• Manufacturer Part Number: PIC18F2221
• Description: 28/40/44-Pin Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology
• Manufacturer: MICROCHIP [Microchip Technology]

2.4
For timing insensitive applications, the RC and RCIO
Oscillator modes offer additional cost savings. The
actual oscillator frequency is a function of several
factors:
• supply voltage
• values of the external resistor (R
• operating temperature
Given the same device, operating voltage, temperature
and component values, there will also be unit-to-unit
frequency variations. These are due to factors such as:
• normal manufacturing variation
• difference in lead frame capacitance between
• variations within the tolerance of limits of R
In the RC Oscillator mode, the oscillator frequency
divided by 4 is available on the OSC2 pin. This signal
may be used for test purposes or to synchronize other
logic. Figure 2-5 shows how the R/C combination is
connected.
FIGURE 2-5:
The RCIO Oscillator mode (Figure 2-6) functions like
the RC mode, except that the OSC2 pin becomes an
additional general purpose I/O pin. The I/O pin
becomes bit 6 of PORTA (RA6).
FIGURE 2-6:
© 2007 Microchip Technology Inc.
C
V
C
V
Recommended values: 3 kΩ ≤ R
Recommended values: 3 kΩ ≤ R
capacitor (C
package types (especially for low C
and C
R
R
EXT
SS
EXT
SS
EXT
EXT
V
V
DD
DD
EXT
RC Oscillator
RA6
EXT
F
OSC
)
/4
RC OSCILLATOR MODE
OSC1
RCIO OSCILLATOR MODE
OSC1
OSC2/CLKO
I/O (OSC2)
20 pF ≤ C
20 pF ≤ C
EXT
EXT
EXT
EXT
EXT
≤ 100 kΩ
≤ 100 kΩ
≤ 300 pF
≤ 300 pF
EXT
PIC18FXXXX
PIC18FXXXX
) and
values)
Internal
Internal
Clock
Clock
EXT
Preliminary
2.5
A Phase Locked Loop (PLL) circuit is provided as an
option for users who wish to use a lower frequency
oscillator circuit or to clock the device up to its highest
rated frequency from a crystal oscillator. This may be
useful for customers who are concerned with EMI due
to high-frequency crystals or users who require higher
clock speeds from an internal oscillator.
2.5.1
The HSPLL mode makes use of the HS mode oscillator
for frequencies up to 10 MHz. A PLL then multiplies the
oscillator output frequency by 4 to produce an internal
clock frequency up to 40 MHz. The PLLEN bit is not
available when this mode is configured as the primary
clock source.
The PLL is only available to the crystal oscillator when
the FOSC3:FOSC0 Configuration bits are programmed
for HSPLL mode (= 0110).
FIGURE 2-7:
2.5.2
The PLL is also available to the internal oscillator block
when the internal oscillator block is configured as the
primary clock source. In this configuration, the PLL is
enabled in software and generates a clock output of up
to 32 MHz. The operation of INTOSC with the PLL is
described in Section 2.6.4 “PLL in INTOSC Modes”.
PIC18F4321 FAMILY
OSC2
OSC1
PLL Frequency Multiplier
(from Configuration Register 1H)
HS Oscillator Enable
HS Mode
HSPLL OSCILLATOR MODE
PLL AND INTOSC
Crystal
Osc
PLL Enable
F
F
IN
OUT
÷4
HSPLL BLOCK DIAGRAM
Comparator
Loop
Filter
Phase
VCO
DS39689E-page 25
SYSCLK