KSZ8842-PMBLAM MICREL [Micrel Semiconductor], KSZ8842-PMBLAM Datasheet - Page 40

• Manufacturer Part Number: KSZ8842-PMBLAM
• Description: 2-Port Ethernet Switch with PCI Interface
• Manufacturer: MICREL [Micrel Semiconductor]

Micrel, Inc.
The following table describes the CFCS register bit fields.
October 2007
26 – 25
23 – 22
20 – 9
5 – 3
Bit
24
21
31
30
29
28
27
8
7
6
Command
Command
Reserved
Reserved
Reserved
Reserved
Status
Status
Status
Status
Status
Status
Status
Status
Type
Default
0x000
000
01
00
0
0
0
0
0
0
0
0
0
0
Data Parity Report
This bit is set when the following conditions are met:
The KSZ8842-PMQL/PMBL asserts parity error PERR_N or it
senses the assertion of PERR_N by another device.
The KSZ8842-PMQL/PMBL operates as a bus master for the
operation that caused the error.
Parity error response (CFCS[6]) is set.
Reserved
66MHz Capable
0 = Not 66MHz capable
Reserved
System Error Enable
When set, the KSZ8842-PMQL/PMBL asserts system error
(SERR_N) when it detects a parity error on the address phase.
Reserved
Parity Error Response
When set, the KSZ8842-PMQL/PMBL asserts fatal bus error after it
detects a parity error.
When reset, any detected parity error is ignored and the KSZ8842-
PMQL/PMBL continues normal operation. Parity checking is
disabled after hardware reset.
Reserved
Description
Detected Parity Error
When set, indicates that the KSZ8842-PMQL/PMBL detected a
parity error, even if parity error handling is disabled in parity error
response (CFCS[6]).
Signal System Error
When set, indicates that the KSZ8842-PMQL/PMBL asserted the
system error SERR_N pin/ball.
Received Master Abort
When set, indicates that the KSZ8842-PMQL/PMBL terminated a
master transaction with master abort.
Received Target Abort
When set, indicates that the KSZ8842-PMQL/PMBL master
transaction was terminated due to a target abort.
Target Abort
This bit is set by KSZ8842-PMQL/PMBL whenever it terminates
with a Target Abort. The CSR registers are all 32-bit Little Endian
format.
For PCI register Read cycles, the KSZ8842-PMQL/PMBL allows
any different combination of CBEN. For PCI register bus cycles,
only byte, word (16-bit), or Dword (32-bit) accesses are allowed.
Any other combination is illegal and is target aborted.
Device Select Timing
Indicates the timing of the assertion of device select(DEVSEL_N).
These bits are fixed at 01, which indicates a middle assertion of
DEVSEL_N.
40
KSZ8842-PMQL/PMBL
M9999-100207-1.5