KSZ8842-PMBLAM MICREL [Micrel Semiconductor], KSZ8842-PMBLAM Datasheet - Page 17

• Manufacturer Part Number: KSZ8842-PMBLAM
• Description: 2-Port Ethernet Switch with PCI Interface
• Manufacturer: MICREL [Micrel Semiconductor]

Micrel, Inc.
October 2007
B4
A4
C3
A3
B3
B2
A2
A1
B1
C1
C2
D1
D2
F2
F1
G2
G1
G3
H1
H2
J1
J2
K1
Ball
Number
INTRN
EECS
P2LED3
EEEN
P1LED3
EEDO
EESK
EEDI
PWRDN
RXP1
RXM1
TXP1
TXM1
RXM2
RXP2
TXM2
TXP2
ISET
X1
X2
RSTN
PAR
FRAMEN
Ball
Name
Opd
Opu
Opd
Ipd
Opd
Opd
Opd
Ipd
Ipu
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
I
O
Ipu
O
I/O
Type
defines the start of each phase. The clock maximum frequency is 33MHz.
Interrupt Request. Active Low signal to host CPU to request an interrupt when any one of the
interrupt conditions occurs in the registers. This pin should be pull-up externally.
EEPROM Chip Select. This signal is used to select an external EEPROM device
Port 2 LED Indicator
See the description in ball B5, B6 and A6.
EEPROM Enable
EEPROM is enabled and connected when this pin is pull-up.
EEPROM is disabled when this pin is pull-down or no connect.
Port 1 LED indicator
See the description in ball C7, A7 and B7.
EEPROM Data Out:
This pin is connected to DI input of the serial EEPROM.
EEPROM Serial Clock:
A 4
EEPROM Data In:
This pin is connected to DO output of the serial EEPROM.
Full-chip power-down. Active Low.
Port 1 physical receive (MDI) or transmit (MDIX) signal (+ differential)
Port 1 physical receive (MDI) or transmit (MDIX) signal (– differential)
Port 1 physical transmit (MDI) or receive (MDIX) signal (+ differential)
Port 1 physical transmit (MDI) or receive (MDIX) signal (– differential)
Port 2 physical receive (MDI) or transmit (MDIX)signal (- differential)
Port 2 physical receive(MDI) or transmit (MDIX) signal (+ differential)
Port 2 physical transmit (MDI) or receive (MDIX) signal (- differential)
Port 2 physical transmit (MDI) or receive (MDIX) signal (+ differential)
Set physical transmit output current.
Pull-down this ball with a 3.01K 1% resistor.
25MHz crystal/oscillator clock connections
Balls (X1, X2) connect to a crystal. If an oscillator is used, X1 connects to a 3.3V tolerant
oscillator and X2 is a no connect.
Note: Clock is ± 50ppm for both crystal and oscillator.
Hardware Reset, Active Low
RSTN will cause the KSZ8842-PMBL to reset all of its functional blocks. RSTN must be
asserted for a minimum duration of 10 ms.
PCI Parity
Even parity computed for PAD [31:0] and CBE[3:0]N, master drives PAR for address and
write data phase, target drives PAR for read data phase.
PCI Cycle Frame
This signal is asserted low to indicate the beginning of the address phase of the bus
transaction and de-asserted before the final transfer of the data phase of the transaction in a
bus master mode. As a target, the device monitors this signal before decoding the address to
check if the current transaction is addressed to it.
Ball Function
µ
s serial output clock to load configuration data from the serial EEPROM.
17
KSZ8842-PMQL/PMBL
M9999-100207-1.5