KSZ8842-PMBLAM MICREL [Micrel Semiconductor], KSZ8842-PMBLAM Datasheet - Page 13

• Manufacturer Part Number: KSZ8842-PMBLAM
• Description: 2-Port Ethernet Switch with PCI Interface
• Manufacturer: MICREL [Micrel Semiconductor]

Micrel, Inc.
October 2007
Pin
Number
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
VDDARX
FRAMEN
VDDATX
Pin
Name
VDDAP
IRDYN
AGND
AGND
AGND
AGND
AGND
AGND
VDDA
RXM1
RXM2
VDDA
RSTN
RXP1
TXM1
RXP2
TXM2
TXP1
TXP2
ISET
PAR
NC
NC
NC
NC
X1
X2
Type
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Ipu
I/O
I/O
I/O
—
—
—
—
O
P
P
P
P
P
O
I
No connect
Analog ground
1.2V analog V
No connect
Physical receive (MDI) or transmit (MDIX)signal (+ differential)
Physical receive (MDI) or transmit (MDIX) signal (– differential)
Analog ground
Physical transmit (MDI) or receive (MDIX) signal (+ differential)
Physical transmit (MDI) or receive (MDIX) signal (– differential)
3.3V analog V
3.3V analog V
Port 2 physical receive (MDI) or transmit (MDIX)signal (- differential)
Port 2 physical receive(MDI) or transmit (MDIX) signal (+ differential)
Analog ground
Port 2 physical transmit (MDI) or receive (MDIX) signal (- differential)
Port 2 physical transmit (MDI) or receive (MDIX) signal (+ differential)
1.2 analog V
Analog ground
No connect
No connect
Set physical transmit output current
Pull-down this pin with a 3.01K 1% resistor to ground.
Analog ground
1.2V analog V
Analog ground
25MHz crystal/oscillator clock connections
Pins (X1, X2) connect to a crystal. If an oscillator is used, X1 connects to a 3.3V
tolerant oscillator and X2 is not connected.
Note: Clock is ±50ppm for both crystal and oscillator.
Hardware Reset, Active Low
RSTN will cause the KSZ8842-PMQL to reset all of its functional blocks. RSTN must be
asserted for a minimum duration of 10 ms.
PCI Parity
Even parity computed for PAD [31:0] and CBE [3:0]N, master drives PAR for address
and write data phase, target drives PAR for read data phase.
PCI Cycle Frame
This signal is asserted low to indicate the beginning of the address phase of the bus
transaction and de-asserted before the final transfer of the data phase of the
transaction in a bus master mode. As a target, the device monitors this signal before
decoding the address to check if the current transaction is addressed to it.
PCI Initiator Ready
As a bus master, this signal is asserted low to indicate valid data phases on PAD [31:0]
during write data phases, indicates it is ready to accept data during read data phases.
As a target, it’ll monitor this IRDYN signal that indicates the master has put the data on
the bus.
Pin Function
DD
DD
DD
DD
DD
for PLL
13
KSZ8842-PMQL/PMBL
M9999-100207-1.5