XCV405E-7BG556I XILINX [Xilinx, Inc], XCV405E-7BG556I Datasheet - Page 69

• Manufacturer Part Number: XCV405E-7BG556I
• Description: Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
• Manufacturer: XILINX [Xilinx, Inc]

Block RAM Switching Characteristics
TBUF Switching Characteristics
JTAG Test Access Port Switching Characteristics
DS025-3 (v2.2) July 17, 2002
Notes:
1.
Sequential Delays
Clock CLK to DOUT output
Setup and Hold Times before Clock CLK
ADDR inputs
DIN inputs
EN input
RST input
WEN input
Clock CLK
Minimum Pulse Width, High
Minimum Pulse Width, Low
CLKA -> CLKB setup time for different ports
Combinatorial Delays
IN input to OUT output
TRI input to OUT output high-impedance
TRI input to valid data on OUT output
TMS and TDI Setup times before TCK
TMS and TDI Hold times after TCK
Output delay from clock TCK to output TDO
Maximum TCK clock frequency
A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed “best-case”, but
if a “0” is listed, there is no positive hold time.
R
Description
Description
(1)
Description
T
Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
T
T
T
T
BWCK
BDCK
BECK
BRCK
BACK
Symbol
T
T
T
T
www.xilinx.com
1-800-255-7778
BPWH
BPWL
BCKO
BCCS
/T
/T
/T
/T
/T
Symbol
BCKA
BCKD
BCKE
BCKR
BCKW
T
T
T
OFF
ON
IO
0.42 / 0
0.42 / 0
0.97 / 0
0.86 / 0
0.9 / 0
0.63
Min
0.6
0.6
1.2
0.05
0.05
Min
0.0
0.9 / 0
0.9 / 0
2.0 / 0
1.8 / 0
1.7 / 0
Speed Grade
2.46
1.2
1.2
2.4
0.092
0.092
T
-8
T
Symbol
Speed Grade
T
0.0
TCKTDO
TCKTAP
-8
F
TAPTK
TCK
1.0 / 0
1.0 / 0
2.2 / 0
2.1 / 0
2.0 / 0
1.35
1.35
3.1
2.7
0.10
0.10
-7
0.0
-7
Value
11.0
4.0
2.0
33
1.1 / 0
1.1 / 0
2.5 / 0
2.3 / 0
2.2 / 0
0.11
0.11
0 .0
3.5
1.5
1.5
3.0
-6
-6
MHz, max
Module 3 of 4
ns, max
ns, min
ns, min
ns, max
ns, max
ns, max
Units
ns, max
ns, min
ns, min
ns, min
ns, min
ns, min
ns, min
ns, min
ns, min
Units
Units
15